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11.发明申请公开(公告)号：US20180349186A1
公开(公告)日：2018-12-06
申请号：US15870764
申请日：2018-01-12
Applicant: Apple Inc.
Inventor： Jeremy C. Andrus , John G. Dorsey , James M. Magee , Daniel A. Chimene , Cyril de la Cropte de Chanterac , Bryan R. Hinch , Aditya Venkataraman , Andrei Dorofeev , Nigel R. Gamble , Russell A. Blaine , Constantin Pistol
Abstract: Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.
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公开(公告)号：US20150347178A1
公开(公告)日：2015-12-03
申请号：US14576963
申请日：2014-12-19
Applicant: Apple Inc.
Inventor： James Michael Magee , Russell A. Blaine , Daniel Allen Chimene , Vishal Patel , Shantonu Sen
IPC: G06F9/48
CPC classification number: G06F9/4881 , G06F1/3206 , G06F1/3287 , G06F9/461 , G06F9/468 , G06F9/4818 , G06F9/50 , G06F9/52 , G06F9/545 , G06F2209/484 , G06F2209/485 , Y02D10/171 , Y02D10/24
Abstract: A method and an apparatus for activity based execution scheduling are described. Activities may be tracked among a plurality of threads belonging to a plurality of processes running in one or more processors. Each thread may be associated with one of the activities. Each activity may be associated with one or more of the threads in one or more of the processes for a data processing task. The activities may be ordered by a priority order. A group of the threads may be identified to be associated with a particular one of the activities with highest priority based on the priority order. A thread may be selected from the identified threads for next scheduled execution in the processors.
Abstract translation: 描述了一种用于基于活动的执行调度的方法和装置。 可以在属于在一个或多个处理器中运行的多个进程的多个线程中跟踪活动。 每个线程可能与其中一个活动相关联。 每个活动可以与用于数据处理任务的一个或多个处理中的一个或多个线程相关联。 活动可按优先顺序排序。 一组线程可以被识别为基于优先级顺序与具有最高优先级的特定活动相关联。 可以从所识别的线程中选择线程以用于处理器中的下一个预定执行。
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公开(公告)号：US10671430B2
公开(公告)日：2020-06-02
申请号：US15836411
申请日：2017-12-08
Applicant: Apple Inc.
Inventor： Daniel A. Steffen , Jainam A. Shah , James M. Magee , Jeremy C. Andrus , Russell A. Blaine
Abstract: Techniques are disclosed relating to inter-process communication. In some embodiments, a kernel receives a notification of a communication to be sent from a first thread of a first application to a second thread of a second application. The kernel provides a reply port to the first thread for receiving a reply to the communication from the second thread. The kernel facilitates sending the communication from the first thread to the second thread. The kernel increases an execution priority of the second thread in response to the kernel determining that the reply port and a destination port associated with the second thread are identified in the communication. In some embodiments, the kernel creates the reply port in response to receiving the notification and, in response to detecting the reply has been communicated to the reply port, decreases the execution priority of the second thread and removes the reply port.
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公开(公告)号：US20180349176A1
公开(公告)日：2018-12-06
申请号：US15870763
申请日：2018-01-12
Applicant: Apple Inc.
Inventor： Jeremy C. Andrus , John G. Dorsey , James M. Magee , Daniel A. Chimene , Cyril de la Cropte de Chanterac , Bryan R. Hinch , Aditya Venkataraman , Andrei Dorofeev , Nigel R. Gamble , Russell A. Blaine , Constantin Pistol
CPC classification number: G06F9/505 , G06F1/206 , G06F1/3206 , G06F1/324 , G06F1/3243 , G06F1/329 , G06F1/3296 , G06F9/268 , G06F9/30145 , G06F9/3851 , G06F9/3891 , G06F9/4856 , G06F9/4881 , G06F9/4893 , G06F9/5044 , G06F9/5094 , G06F9/54 , G06F2209/501 , G06F2209/5018 , G06F2209/509
Abstract: Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.
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公开(公告)号：US20170269967A1
公开(公告)日：2017-09-21
申请号：US15444186
申请日：2017-02-27
Applicant: Apple Inc.
Inventor： Daniel A. Steffen , Matthew W. Wright , Russell A. Blaine , Daniel A. Chimene , Kevin J. Van Vechten , Thomas B. Duffy
CPC classification number: G06F9/4893 , G06F9/4881 , G06F9/5038 , G06F2209/5021 , Y02D10/22
Abstract: In one embodiment, tasks executing on a data processing system can be associated with a Quality of Service (QoS) classification that is used to determine the priority values for multiple subsystems of the data processing system. The QoS classifications are propagated when tasks interact and the QoS classes are interpreted a multiple levels of the system to determine the priority values to set for the tasks. In one embodiment, one or more sensors coupled with the data processing system monitor a set of system conditions that are used in part to determine the priority values to set for a QoS class.
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Patent Agency Ranking
公开(公告)号：US09665398B2
公开(公告)日：2017-05-30
申请号：US14576963
申请日：2014-12-19
Applicant: Apple Inc.
Inventor： James Michael Magee , Russell A. Blaine , Daniel Allen Chimene , Vishal Patel , Shantonu Sen
CPC classification number: G06F9/4881 , G06F1/3206 , G06F1/3287 , G06F9/461 , G06F9/468 , G06F9/4818 , G06F9/50 , G06F9/52 , G06F9/545 , G06F2209/484 , G06F2209/485 , Y02D10/171 , Y02D10/24
Abstract: A method and an apparatus for activity based execution scheduling are described. Activities may be tracked among a plurality of threads belonging to a plurality of processes running in one or more processors. Each thread may be associated with one of the activities. Each activity may be associated with one or more of the threads in one or more of the processes for a data processing task. The activities may be ordered by a priority order. A group of the threads may be identified to be associated with a particular one of the activities with highest priority based on the priority order. A thread may be selected from the identified threads for next scheduled execution in the processors.
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公开(公告)号：US09348645B2
公开(公告)日：2016-05-24
申请号：US14576917
申请日：2014-12-19
Applicant: Apple Inc.
Inventor： James Michael Magee , Russell A. Blaine , Daniel A. Chimene , James McIlree , Vishal Patel , Daniel Andreas Steffen , Kevin James Van Vechten
CPC classification number: G06F9/4881 , G06F1/3206 , G06F1/3287 , G06F9/461 , G06F9/468 , G06F9/4818 , G06F9/50 , G06F9/52 , G06F9/545 , G06F2209/484 , G06F2209/485 , Y02D10/171 , Y02D10/24
Abstract: A method and an apparatus for priority donations among different processes are described. A first process running with a first priority may receive a request from a second process running with a second priority to perform a data processing task for the second process. A dependency relationship may be identified between the first process and a third process running with a third priority performing separate data processing task. The dependency relationship may indicate that the data processing task is to be performed via the first process subsequent to completion of the separate data processing task via the third process. The third process may be updated with the second priority to complete the separate data processing task. The first process may perform the data processing task with the second priority for the second process.
Abstract translation: 描述了用于不同处理之间的优先捐赠的方法和装置。 以第一优先级运行的第一进程可以从具有第二优先级的第二进程接收请求，以执行第二进程的数据处理任务。 可以在第一进程和执行分开的数据处理任务的第三优先级运行的第三进程之间识别依赖关系。 依赖关系可以指示经由第三处理完成单独的数据处理任务之后，经由第一处理执行数据处理任务。 可以用第二优先级来更新第三进程以完成单独的数据处理任务。 第一进程可以执行具有第二进程的第二优先级的数据处理任务。
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公开(公告)号：US20150347177A1
公开(公告)日：2015-12-03
申请号：US14576917
申请日：2014-12-19
Applicant: Apple Inc.
Inventor： James Michael Magee , Russell A. Blaine , Daniel A. Chimene , James McIlree , Vishal Patel , Daniel Andreas Steffen , Kevin James Van Vechten
IPC: G06F9/48
CPC classification number: G06F9/4881 , G06F1/3206 , G06F1/3287 , G06F9/461 , G06F9/468 , G06F9/4818 , G06F9/50 , G06F9/52 , G06F9/545 , G06F2209/484 , G06F2209/485 , Y02D10/171 , Y02D10/24
Abstract: A method and an apparatus for priority donations among different processes are described. A first process running with a first priority may receive a request from a second process running with a second priority to perform a data processing task for the second process. A dependency relationship may be identified between the first process and a third process running with a third priority performing separate data processing task. The dependency relationship may indicate that the data processing task is to be performed via the first process subsequent to completion of the separate data processing task via the third process. The third process may be updated with the second priority to complete the separate data processing task. The first process may perform the data processing task with the second priority for the second process.
Abstract translation: 描述了用于不同处理之间的优先捐赠的方法和装置。 以第一优先级运行的第一进程可以从具有第二优先级的第二进程接收请求，以执行第二进程的数据处理任务。 可以在第一进程和执行分开的数据处理任务的第三优先级运行的第三进程之间识别依赖关系。 依赖关系可以指示经由第三处理完成单独的数据处理任务之后，经由第一处理执行数据处理任务。 可以用第二优先级来更新第三进程以完成单独的数据处理任务。 第一进程可以执行具有第二进程的第二优先级的数据处理任务。
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公开(公告)号：US11670252B2
公开(公告)日：2023-06-06
申请号：US16888606
申请日：2020-05-29
Applicant: Apple Inc.
Inventor： Simon M. Douglas , Ross Thompson , Russell A. Blaine , Arthur L. Spence , Brad W. Simeral , Giovanni M. Agnoli , Chendi Zhang , Jacob Z. Weiss , Yiqiang Nie , Brent W. Schorsch
IPC: G06F1/3218 , G09G3/36
CPC classification number: G09G3/3611 , G06F1/3218 , G09G2330/021 , G09G2360/18
Abstract: A device implementing a system for displaying an image includes a processor configured to, generate, during a first power state of a device, a data structure specifying image frames and a respective display time for each of the image frames, and retrieve, during a second power state of the device and from the data structure, an image frame based on the respective display time for the image frame. The at least one processor is further configured to display, during a third power state of the device, the retrieved image frame on a display of the device.
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公开(公告)号：US11086800B2
公开(公告)日：2021-08-10
申请号：US16882087
申请日：2020-05-22
Applicant: Apple Inc.
Inventor： Jeremy C. Andrus , Joseph R. Auricchio , Russell A. Blaine , Daniel A. Chimene , Simon M. Douglas , Landon J. Fuller , Yevgen Goryachok , John K. Kim-Biggs , Arnold S. Liu , James M. Magee , Daniel A. Steffen , Roberto G. Yepez
Abstract: Embodiments described herein provide techniques to manage drivers in a user space in a data processing system. One embodiment provides a data processing system configured perform operations, comprising discovering a hardware device communicatively coupled to the communication bus, launching a user space driver daemon, establishing an inter-process communication (IPC) link between a first proxy interface for the user space driver daemon and a second proxy interface for a server process in a kernel space, receiving, at the first proxy interface, an access right to enable access to a memory buffer in the kernel space, and relaying an access request for the memory buffer from the user space driver daemon via a third-party proxy interface to enable the user space driver daemon to access the memory buffer, the access request based on the access right.
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