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公开(公告)号：US20230380170A1
公开(公告)日：2023-11-23
申请号：US18319876
申请日：2023-05-18
Applicant: Applied Materials, Inc.
Inventor： Hsiang Yu Lee , Pradeep K. Subrahmanyan
CPC classification number: H10B43/35 , C30B29/06 , C30B29/16 , C30B29/38 , C30B29/68 , C30B33/08 , H10B43/10 , H10B43/27
Abstract: A three-dimensional NAND flash memory structure may include solid channel cores of epitaxial silicon that are grown directly from a silicon substrate reference. The alternating oxide-nitride material layers may be formed as a stack, and a channel hole may be etched through the material layers that extends down to the silicon substrate. A tunneling layer may be formed around the channel hole to contact the alternating material layers, and an epitaxial silicon core may be grown from the silicon substrate up through the channel holes. In some implementations, support structures may be formed in channel holes or in slits of the memory array to provide physical support while the epitaxial silicon cores are grown through the channels.
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Patent Agency Ranking
公开(公告)号：US20220344282A1
公开(公告)日：2022-10-27
申请号：US17730527
申请日：2022-04-27
Applicant: Applied Materials, Inc.
Inventor： Pradeep K. Subrahmanyan , Sean S. Kang , Sony Varghese
Abstract: Provided are methods of reducing the stress of a semiconductor wafer. A wafer map of a free-standing wafer is created using metrology tools. The wafer map is then converted into a power spectral density (PSD) using a spatial frequency scale. The fundamental component of bow is then compensated with a uniform film, e.g., silicon nitride (SiN), deposited on the back side of the wafer.
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公开(公告)号：US20240387286A1
公开(公告)日：2024-11-21
申请号：US18664611
申请日：2024-05-15
Applicant: Applied Materials, Inc.
Inventor： San-Kuei Lin , Pradeep K. Subrahmanyan
IPC: H01L21/8238 , H01L21/762 , H01L27/092 , H01L29/66
Abstract: Methods of manufacturing electronic devices are described. Embodiments of the present disclosure advantageously provide methods of manufacturing electronic devices, e.g., complementary field-effect transistors (CFETs) that meet reduced thickness, reduced leakage, lower thermal budget, and Vt requirements (including multi-Vt), and have improved device performance and reliability. Some embodiments of the methods include conventional dipole engineering techniques such as dipole first processes and/or dipole last processes without the need for repairing the interfacial layer after treatment (in dipole first processes) or repairing the high-K dielectric layer after the annealing process (in dipole last processes).
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公开(公告)号：US20240365545A1
公开(公告)日：2024-10-31
申请号：US18639572
申请日：2024-04-18
Applicant: Applied Materials, Inc.
Inventor： Hsiang Yu Lee , Pradeep K. Subrahmanyan
Abstract: Disclosed are approaches for wordline contact formation for 3D NAND devices. Methods may include providing a film stack of alternating first layers and second layers, forming a first lithography mask over the film stack, and performing a first series of alternating lithography and etch processes to form an array of contact opening pairs in the film stack, wherein an opening through the first lithography mask is expanded in a first direction following each etch process, and wherein a depth of the array of contact opening pairs varies in the first direction. The method may further include forming a second lithography mask over the film stack, and performing a second series of alternating lithography and etch processes, wherein an opening through the second lithography mask is expanded in a second direction following each etch process, and wherein the depth of the array of contact opening pairs varies in the second direction.
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公开(公告)号：US20240363150A1
公开(公告)日：2024-10-31
申请号：US18640422
申请日：2024-04-19
Applicant: Applied Materials, Inc.
Inventor： Hsiang Yu Lee , Pradeep K. Subrahmanyan
CPC classification number: G11C5/063 , G11C16/0483 , H01L21/0274 , H10B41/10 , H10B41/35 , H10B43/10 , H10B43/35
Abstract: Disclosed are approaches for wordline contact formation for 3D NAND devices. Methods may include providing a film stack of alternating first layers and second layers, forming a first lithography mask over the film stack, and performing a first series of alternating lithography and etch processes to form an array of contact opening pairs in the film stack, wherein an opening through the first lithography mask is expanded in a first direction following each etch process, and wherein a depth of the array of contact opening pairs varies in the first direction. The method may further include forming a second lithography mask over the film stack, and performing a second series of alternating lithography and etch processes, wherein an opening through the second lithography mask is expanded in a second direction following each etch process, and wherein the depth of the array of contact opening pairs varies in the second direction.
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公开(公告)号：US20230413569A1
公开(公告)日：2023-12-21
申请号：US18319869
申请日：2023-05-18
Applicant: Applied Materials, Inc.
Inventor： Hsiang Yu Lee , Pradeep K. Subrahmanyan
CPC classification number: H10B43/35 , C30B29/06 , C30B29/38 , H10B43/27 , C30B29/68 , C30B33/08 , H10B43/10 , C30B29/16
Abstract: A three-dimensional NAND flash memory structure may include solid channel cores of epitaxial silicon that are grown directly from a silicon substrate reference. The alternating oxide-nitride material layers may be formed as a stack, and a channel hole may be etched through the material layers that extends down to the silicon substrate. A tunneling layer may be formed around the channel hole to contact the alternating material layers, and an epitaxial silicon core may be grown from the silicon substrate up through the channel holes. In some implementations, support structures may be formed in channel holes or in slits of the memory array to provide physical support while the epitaxial silicon cores are grown through the channels.
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