公开(公告)号：US20230409517A1

公开(公告)日：2023-12-21

申请号：US17841720

申请日：2022-06-16

Applicant: BAE Systems Information and Electronic Systems Integration Inc.

Inventor： David D. Moser ,  Christopher N. Peters ,  Daniel L. Stanley ,  Umair Aslam ,  Elizabeth J. Williams ,  Angelica Sunga

IPC: G06F15/78 ,  G06F13/38 ,  G06F13/16

CPC classification number: G06F15/7817 ,  G06F13/385 ,  G06F15/7871 ,  G06F13/1668

Abstract: An encapsulation block for a digital signal processing (DSP) block. The encapsulation block includes DSP block having an input terminal, an output terminal, and an input clock. The encapsulation block also includes pacing control network operatively connected with the input terminal, the output terminal, and the input clock of the DSP block. The input terminal of the DSP block is configured to receive a samples-in data stream inputted at a predefined clock period defined by the input clock. The output terminal of the DSP block is configured to receive a samples-out data stream outputted at a predefined paced parameter. The pacing control network is configured to control data flow at the samples-in data stream and the samples-out data stream independently of the DSP block.

公开(公告)号：US11108383B1

公开(公告)日：2021-08-31

申请号：US17025049

申请日：2020-09-18

Applicant: BAE Systems Information and Electronic Systems Integration Inc.

Inventor： David D. Moser ,  Michael J. Frack ,  Mark R. Shaffer ,  Daniel L. Stanley

IPC: H03K5/13 ,  H03K5/01 ,  H03K19/21 ,  G06F1/06 ,  G06F1/08 ,  G11C19/28 ,  H03K5/00

Abstract: A clock phase control circuit includes a clock input gate module, first and second shift register divider modules, and a multiplexer. The clock input gate module is configured to produce, based on an oscillating input clock signal, first and second intermediate clock signals. The first shift register divider module is configured to produce at least one first phase clock signal based on the first intermediate clock signal, where the at least one first phase clock signal has a different frequency than the first intermediate clock signal. The second shift register divider module is configured to produce at least one second phase clock signal based on the second intermediate clock signal, where the at least one second phase clock signal has a different frequency than the second intermediate clock signal. The multiplexer is configured to produce an output clock signal by selecting one of the first or second phase clock signals.

公开(公告)号：US20200051961A1

公开(公告)日：2020-02-13

申请号：US16057204

申请日：2018-08-07

Applicant: BAE Systems Information and Electronic Systems Integration Inc.

Inventor： Dale A. Rickard ,  Jason F. Ross ,  John T. Matta ,  Richard J. Ferguson ,  Alan F. Dennis ,  Joseph R. Marshall, JR. ,  Daniel L. Stanley

IPC: H01L25/16 ,  H01L23/498 ,  H01L23/00 ,  H01L27/112 ,  H01L25/00

Abstract: An MCM-HIC device flexibly adds enhanced features to a VLSI “core” IC that are not directly supported by the core IC, such as unsupported communication protocols and/or support of cold spare operation. The core IC is mounted on an interconnecting substrate together with at least one “chiplet” that provides the required feature(s). The chiplet can be programmable. The chiplet can straddle a boundary of an interposer region of the substrate that provides higher density interconnections at lower currents. The disclosed method can include selecting a core IC and at least one active, passive, or “mixed” chiplet, configuring a substrate, and installing the core IC and chiplet(s) on the substrate. In embodiments, the core IC and/or chiplet(s) can be modified before assembly to obtain the desired result. Cost can be reduced by pre-designing and, in embodiments, pre-manufacturing the chiplets and modified core ICs in cost-effective quantities.