公开(公告)号：US07491308B2

公开(公告)日：2009-02-17

申请号：US11123268

申请日：2005-05-05

Applicant: Homayoun Talieh ,  Cyprian Uzoh ,  Bulent M. Basol

Inventor： Homayoun Talieh ,  Cyprian Uzoh ,  Bulent M. Basol

IPC: C25D5/00 ,  C25B9/00

CPC classification number: B23H3/04 ,  B23H5/08 ,  C25D5/08 ,  C25D17/00 ,  C25D17/001 ,  C25D17/005 ,  C25F7/00 ,  H01L21/2885

Abstract: Substantially uniform deposition of conductive material on a surface of a substrate, which substrate includes a semiconductor wafer, from an electrolyte containing the conductive material can be provided by way of a particular device which includes first and second conductive elements. The first conductive element can have multiple electrical contacts, of identical or different configurations, or may be in the form of a conductive pad, and can contact or otherwise electrically interconnect with the substrate surface over substantially all of the substrate surface. Upon application of a potential between the first and second conductive elements while the electrolyte makes physical contact with the substrate surface and the second conductive element, the conductive material is deposited on the substrate surface. It is possible to reverse the polarity of the voltage applied between the anode and the cathode so that electro-etching of deposited conductive material can be performed.

Abstract translation: 可以通过包括第一和第二导电元件的特定装置来提供导电材料在包含导电材料的电解质的衬底的包括半导体晶片的表面上的基本均匀沉积。 第一导电元件可以具有相同或不同构造的多个电触点，或者可以是导电焊盘的形式，并且可以在基本上所有的衬底表面上与衬底表面接触或以其他方式电互连。 当在电解质与衬底表面和第二导电元件物理接触的同时在第一和第二导电元件之间施加电势时，导电材料沉积在衬底表面上。 可以使施加在阳极和阴极之间的电压的极性反转，从而可以对沉积的导电材料进行电蚀刻。

公开(公告)号：US07311811B2

公开(公告)日：2007-12-25

申请号：US10826219

申请日：2004-04-16

Applicant: Homayoun Talieh ,  Cyprian Uzoh ,  Bulent M. Basol

Inventor： Homayoun Talieh ,  Cyprian Uzoh ,  Bulent M. Basol

IPC: C25F3/02

CPC classification number: B23H3/04 ,  B23H5/08 ,  C25D5/08 ,  C25D17/00 ,  C25D17/001 ,  C25D17/005 ,  C25F7/00 ,  H01L21/2885

Abstract: Substantially uniform deposition of conductive material on a surface of a substrate, which substrate includes a semiconductor wafer, from an electrolyte containing the conductive material can be provided by way of a particular device which includes first and second conductive elements. The first conductive element can have multiple electrical contacts, of identical or different configurations, or may be in the form of a conductive pad, and can contact or otherwise electrically interconnect with the substrate surface over substantially all of the substrate surface. Upon application of a potential between the first and second conductive elements while the electrolyte makes physical contact with the substrate surface and the second conductive element, the conductive material is deposited on the substrate surface. It is possible to reverse the polarity of the voltage applied between the anode and the cathode so that electro-etching of deposited conductive material can be performed.

Abstract translation: 可以通过包括第一和第二导电元件的特定装置来提供导电材料在包含导电材料的电解质的衬底的包括半导体晶片的表面上的基本均匀沉积。 第一导电元件可以具有相同或不同构造的多个电触点，或者可以是导电焊盘的形式，并且可以在基本上所有的衬底表面上与衬底表面接触或以其他方式电互连。 当在电解质与衬底表面和第二导电元件物理接触的同时在第一和第二导电元件之间施加电势时，导电材料沉积在衬底表面上。 可以使施加在阳极和阴极之间的电压的极性反转，从而可以对沉积的导电材料进行电蚀刻。

公开(公告)号：US06932896B2

公开(公告)日：2005-08-23

申请号：US09982558

申请日：2001-10-17

Applicant: Bulent M. Basol ,  Cyprian Uzoh ,  Homayoun Talieh

Inventor： Bulent M. Basol ,  Cyprian Uzoh ,  Homayoun Talieh

IPC: B08B1/04 ,  B24B37/04 ,  B24B53/00 ,  B24B53/007 ,  C25D5/22 ,  C25D7/12 ,  C25F3/16 ,  H01L21/288 ,  H01L21/304 ,  H01L21/768

CPC classification number: B24B53/017 ,  B24B37/04 ,  B24B53/001 ,  C25D5/22 ,  C25D17/001 ,  H01L21/2885 ,  H01L21/7684 ,  H01L21/76877

Abstract: Systems and methods to remove or lessen the size of metal particles that have formed on, and to limit the rate at which metal particles form or grow on, workpiece surface influencing devices used during electrodeposition are presented. According to an exemplary method, the workpiece surface influencing device is occasionally placed in contact with a conditioning substrate coated with an inert material, and the bias applied to the electrodeposition system is reversed. According to another exemplary method, the workpiece surface influencing device is conditioned using mechanical contact members, such as brushes, and conditioning of the workpiece surface influencing device occurs, for example, through physical brushing of the workpiece surface influencing device with the brushes. According to a further exemplary method, the workpiece surface influencing device is rotated in different direction during electrodeposition.

Abstract translation: 提出了用于去除或减小在电沉积期间使用的工件表面影响装置上形成金属颗粒的尺寸并限制金属颗粒形成或生长的速率的系统和方法。 根据示例性的方法，工件表面影响装置偶尔地与涂覆有惰性材料的调理基板接触，并且施加到电沉积系统的偏压被反转。 根据另一示例性方法，使用诸如刷子的机械接触构件对工件表面影响装置进行调节，并且例如通过用刷子物理刷刷工件表面影响装置来发生工件表面影响装置的调节。 根据另一示例性方法，在电沉积期间，工件表面影响装置在不同方向上旋转。

公开(公告)号：US06815354B2

公开(公告)日：2004-11-09

申请号：US10282976

申请日：2002-10-28

Applicant: Cyprian Uzoh ,  Bulent M. Basol ,  Homayoun Talieh

Inventor： Cyprian Uzoh ,  Bulent M. Basol ,  Homayoun Talieh

IPC: H01L2100

CPC classification number: H01L21/7684 ,  H01L21/76885 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A process for forming a conductive structure on a substrate is provided. The substrate has a copper seed layer that is partially exposed through a plurality of openings in a masking layer such as a photoresist. The masking layer is formed on the seed layer. The process electroplates copper through the openings and onto the seed layer. During the copper electroplating process the surface of the masking layer is mechanically swept. The process forms planar conductive material deposits filling the plurality of holes in the masking layer. The upper ends of the conductive deposits are substantially co-planar.

Abstract translation: 提供了在基板上形成导电结构的工艺。 衬底具有通过诸如光致抗蚀剂的掩模层中的多个开口部分暴露的铜籽晶层。 掩蔽层形成在种子层上。 该方法通过开口将铜电镀到种子层上。 在铜电镀过程中，屏蔽层的表面被机械扫掠。 该过程形成填充掩模层中的多个孔的平面导电材料沉积物。 导电沉积物的上端基本上是共面的。

公开(公告)号：US06610190B2

公开(公告)日：2003-08-26

申请号：US09760757

申请日：2001-01-17

Applicant: Bulent M. Basol ,  Cyprian Uzoh ,  Homayoun Talieh

Inventor： Bulent M. Basol ,  Cyprian Uzoh ,  Homayoun Talieh

IPC: C25D508

CPC classification number: C25D5/02 ,  C25D7/123 ,  C25D17/001 ,  H01L21/2885 ,  H01L21/3212 ,  H01L21/76877

Abstract: A system for depositing materials on a surface of a wafer or removing materials from the surface of a wafer includes an electrode, a shaping plate, a liquid solution contained between the electrode and the wafer surface, and electrical contact members contacting selected locations on the wafer surface. The shaping plate is supported between the electrode and the wafer surface such that an upper surface of the shaping plate faces the wafer surface. The shaping plate can have a plurality of channels where each puts the wafer surface in a fluid communication with the electrode. The electrical contact members contact the selected locations on the wafer surface through a recessed edge of the shaping plate such that when the wafer is rotated, the selected contact locations move over the shaping plate and are plated under an applied potential. Advantages of the invention include substantially full surface treatment of the wafer.

Abstract translation: 用于在晶片的表面上沉积材料或从晶片表面去除材料的系统包括电极，成形板，包含在电极和晶片表面之间的液体溶液以及与晶片上的选定位置接触的电接触元件 表面。 成形板支撑在电极和晶片表面之间，使得成形板的上表面面向晶片表面。 成形板可以具有多个通道，其中每个通道将晶片表面与电极流体连通。 电接触构件通过成形板的凹入边缘接触晶片表面上的选定位置，使得当晶片旋转时，所选择的接触位置在成形板上移动并在施加电位下进行电镀。 本发明的优点包括晶片的基本全表面处理。

公开(公告)号：US06497800B1

公开(公告)日：2002-12-24

申请号：US09685934

申请日：2000-10-11

Applicant: Homayoun Talieh ,  Cyprian Uzoh ,  Bulent M. Basol

Inventor： Homayoun Talieh ,  Cyprian Uzoh ,  Bulent M. Basol

IPC: C25D1700

CPC classification number: B23H3/04 ,  B23H5/08 ,  C25D5/08 ,  C25D17/00 ,  C25D17/001 ,  C25D17/005 ,  C25F7/00 ,  H01L21/2885

Abstract: Substantially uniform deposition of conductive material on a surface of a substrate, which substrate includes a semiconductor wafer, from an electrolyte containing the conductive material can be provided by way of a particular device which includes first and second conductive elements. The first conductive element can have multiple electrical contacts, of identical or different configurations, or may be in the form of a conductive pad, and can contact or otherwise electrically interconnect with the substrate surface over substantially all of the substrate surface. Upon application of a potential between the first and second conductive elements while the electrolyte makes physical contact with the substrate surface and the second conductive element, the conductive material is deposited on the substrate surface. It is possible to reverse the polarity of the voltage applied between the anode and the cathode so that electro-etching of deposited conductive material can be performed.

Abstract translation: 可以通过包括第一和第二导电元件的特定装置来提供导电材料在包含导电材料的电解质的衬底的包括半导体晶片的表面上的基本均匀沉积。 第一导电元件可以具有相同或不同构造的多个电触点，或者可以是导电焊盘的形式，并且可以在基本上所有的衬底表面上与衬底表面接触或以其他方式电互连。 当在电解质与衬底表面和第二导电元件物理接触的同时在第一和第二导电元件之间施加电势时，导电材料沉积在衬底表面上。 可以使施加在阳极和阴极之间的电压的极性反转，从而可以对沉积的导电材料进行电蚀刻。

公开(公告)号：US08609540B2

公开(公告)日：2013-12-17

申请号：US13164448

申请日：2011-06-20

Applicant: Cyprian Uzoh ,  Belgacem Haba ,  Craig Mitchell

Inventor： Cyprian Uzoh ,  Belgacem Haba ,  Craig Mitchell

IPC: H01L21/32

CPC classification number: H01L23/528 ,  H01L21/2885 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76852 ,  H01L21/76868 ,  H01L21/76873 ,  H01L21/76879 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53238 ,  H01L24/13 ,  H01L24/14 ,  H01L2221/1094 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/14181 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: Methods and apparatus for forming a semiconductor device are provided which may include any number of features. One feature is a method of forming an interconnect structure that results in the interconnect structure having a top surface and portions of the side walls of the interconnect structure covered in a dissimilar material. In some embodiments, the dissimilar material can be a conductive material or a nano-alloy. The interconnect structure can be formed by removing a portion of the interconnect structure, and covering the interconnect structure with the dissimilar material. The interconnect structure can comprise a damascene structure, such as a single or dual damascene structure, or alternatively, can comprise a silicon-through via (TSV) structure.

Abstract translation: 提供了用于形成半导体器件的方法和装置，其可以包括任何数量的特征。 一个特征是形成互连结构的方法，其导致互连结构具有覆盖在不同材料中的互连结构的顶表面和侧壁的部分。 在一些实施例中，异种材料可以是导电材料或纳米合金。 互连结构可以通过去除互连结构的一部分并且用不同材料覆盖互连结构来形成。 互连结构可以包括镶嵌结构，例如单镶嵌结构或双镶嵌结构，或者可以包括硅通孔（TSV）结构。

公开(公告)号：US20060219573A1

公开(公告)日：2006-10-05

申请号：US11445594

申请日：2006-06-01

Applicant: Cyprian Uzoh ,  Homayoun Talieh ,  Bulent Basol ,  Douglas Young

Inventor： Cyprian Uzoh ,  Homayoun Talieh ,  Bulent Basol ,  Douglas Young

IPC: B23H3/00

CPC classification number: B24B37/20 ,  B24B37/046 ,  B24B37/24 ,  B24B37/26 ,  C25D5/06 ,  C25D17/001 ,  C25D17/14 ,  C25F7/00 ,  H01L21/2885 ,  H01L21/76877

Abstract: The present invention relates to methods and apparatus for plating a conductive material on a semiconductor substrate by rotating pad or blade type objects in close proximity to the substrate, thereby eliminating/reducing dishing and voids. This is achieved by providing pad or blade type objects mounted on cylindrical anodes or rollers and applying the conductive material to the substrate using the electrolyte solution disposed on or through the pads, or on the blades. In one embodiment of the invention, the pad or blade type objects are mounted on the cylindrical anodes and rotated about a first axis while the workpiece may be stationary or rotate about a second axis, and metal from the electrolyte solution is deposited on the workpiece when a potential difference is applied between the workpiece and the anode. In another embodiment of the present invention, the plating apparatus includes an anode plate spaced apart from the cathode workpiece. Upon application of power to the anode plate and the cathode workpiece, the electrolyte solution disposed in the plating apparatus is used to deposit the conductive material on the workpiece surface using cylindrical rollers having the pad or blade type objects.

Abstract translation: 本发明涉及通过旋转靠近基板的垫片或刀片型物体来在半导体衬底上镀覆导电材料的方法和装置，从而消除/减少凹陷和空隙。 这通过提供安装在圆柱形阳极或辊子上的垫片或刀片型物体，并使用设置在垫片上或穿过垫片上的电解质溶液将导电材料施加到衬底来实现。 在本发明的一个实施例中，衬垫或刀片型物体安装在圆柱形阳极上并围绕第一轴线旋转，同时工件可以是静止的或围绕第二轴线旋转，并且来自电解质溶液的金属沉积在工件上， 在工件和阳极之间施加电位差。 在本发明的另一实施例中，电镀装置包括与阴极工件间隔开的阳极板。 在向阳极板和阴极工件施加电力时，使用设置在电镀装置中的电解液将导电材料沉积在工件表面上，使用具有焊盘或刀片型物体的圆柱形辊。

公开(公告)号：US20060070885A1

公开(公告)日：2006-04-06

申请号：US11295014

申请日：2005-12-06

Applicant: Cyprian Uzoh ,  Homayoun Talieh ,  Bulent Basol

Inventor： Cyprian Uzoh ,  Homayoun Talieh ,  Bulent Basol

IPC: C25D5/02 ,  C25D5/48

CPC classification number: C25D5/00 ,  C23C18/1608 ,  C23C18/165 ,  C23C18/1651 ,  C23C18/1653 ,  C23C18/1696 ,  C23C18/1848 ,  C23C18/31 ,  C25D5/02 ,  C25D5/10 ,  C25D5/22 ,  C25D5/34 ,  H01L21/2885 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76865 ,  H01L21/76871 ,  H01L21/76874 ,  H01L21/76876 ,  H01L21/76879 ,  H01L21/76885 ,  H01L24/11 ,  H01L2221/1089 ,  H01L2224/13099 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01016 ,  H01L2924/01019 ,  H01L2924/01021 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01057 ,  H01L2924/0106 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/3011

Abstract: The present invention relates to a method for fabricating high performance chip interconnects and packages by providing methods for depositing a conductive material in cavities of a substrate in a more efficient and time saving manner. This is accomplished by selectively removing portions of a seed layer from a top surface of a substrate and then depositing a conductive material in the cavities of the substrate, where portions of the seed layer remains in the cavities. Another method includes forming an oxide layer on the top surface of the substrate such that the conductive material can be deposited in the cavities without the material being formed on the top surface of the substrate. The present invention also discloses methods for forming multi-level interconnects and the corresponding structures.

公开(公告)号：US06974769B2

公开(公告)日：2005-12-13

申请号：US10663318

申请日：2003-09-16

Applicant: Bulent Basol ,  Homayoun Talieh ,  Cyprian Uzoh

Inventor： Bulent Basol ,  Homayoun Talieh ,  Cyprian Uzoh

IPC: H01L21/768 ,  H01L21/4763

CPC classification number: H01L21/7684

Abstract: Conductive structures in features of an insulator layer on a substrate are fabricated by a particular process. In this process, a layer of conductive material is applied over the insulator layer so that the layer of conductive material covers field regions adjacent the features and fills in the features themselves. A grain size differential between the conductive material which covers the field regions and the conductive material which fills in the features is then established by annealing the layer of conductive material. Excess conductive material is then removed to uncover the field regions and leave the conductive structures. The layer of conductive material is applied so as to define a first layer thickness over the field regions and a second layer thickness in and over the features. These thicknesses are dimensioned such that d1≦0.5d2, with d1 being the first layer thickness and d2 being the second layer thickness. Preferably, the first and second layer thicknesses are dimensioned such that d1≦0.3d2.

Abstract translation: 通过特定的工艺制造衬底上的绝缘体层的特征的导电结构。 在该过程中，将导电材料层施加在绝缘体层上，使得导电材料层覆盖与特征相邻的场区域并填充特征本身。 然后通过退火导电材料层来建立覆盖场区的导电材料与填充特征的导电材料之间的晶粒尺寸差。 然后去除过量的导电材料以露出场区并留下导电结构。 施加导电材料层以在场区域上限定第一层厚度，并且在特征中和之上限定第二层厚度。 这些厚度的尺寸使得其中d 1是第一层厚度，d 2 <2 < / SUB>为第二层厚度。 优选地，第一层厚度和第二层厚度的尺寸被确定为使得d 1 = 0.3D 2。