公开(公告)号：US20190261955A1

公开(公告)日：2019-08-29

申请号：US16404672

申请日：2019-05-06

Applicant: Butterfly Network, Inc.

Inventor： Kailiang Chen ,  Nevada J. Sanchez ,  Susan A. Alie ,  Tyler S. Ralston ,  Jonathan M. Rothberg ,  Keith G. Fife ,  Joseph Lutsky

IPC: A61B8/08 ,  H04B11/00

Abstract: Aspects of the technology described herein relate to an ultrasound device including a first die that includes an ultrasonic transducer, a first application-specific integrated circuit (ASIC) that is bonded to the first die and includes a pulser, and a second ASIC in communication with the second ASIC that includes integrated digital receive circuitry. In some embodiments, the first ASIC may be bonded to the second ASIC and the second ASIC may include analog processing circuitry and an analog-to-digital converter. In such embodiments, the second ASIC may include a through-silicon via (TSV) facilitating communication between the first ASIC and the second ASIC. In some embodiments, SERDES circuitry facilitates communication between the first ASIC and the second ASIC and the first ASIC includes analog processing circuitry and an analog-to-digital converter. In some embodiments, the technology node of the first ASIC is different from the technology node of the second ASIC.

公开(公告)号：US20190261954A1

公开(公告)日：2019-08-29

申请号：US16404665

申请日：2019-05-06

Applicant: Butterfly Network, Inc.

Inventor： Kailiang Chen ,  Nevada J. Sanchez ,  Susan A. Alie ,  Tyler S. Ralston ,  Jonathan M. Rothberg ,  Keith G. Fife ,  Joseph Lutsky

IPC: A61B8/08 ,  H04B11/00

Abstract: Aspects of the technology described herein relate to an ultrasound device including a first die that includes an ultrasonic transducer, a first application-specific integrated circuit (ASIC) that is bonded to the first die and includes a pulser, and a second ASIC in communication with the second ASIC that includes integrated digital receive circuitry. In some embodiments, the first ASIC may be bonded to the second ASIC and the second ASIC may include analog processing circuitry and an analog-to-digital converter. In such embodiments, the second ASIC may include a through-silicon via (TSV) facilitating communication between the first ASIC and the second ASIC. In some embodiments, SERDES circuitry facilitates communication between the first ASIC and the second ASIC and the first ASIC includes analog processing circuitry and an analog-to-digital converter. In some embodiments, the technology node of the first ASIC is different from the technology node of the second ASIC.