公开(公告)号：US09607851B2

公开(公告)日：2017-03-28

申请号：US14411978

申请日：2013-07-25

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Qiang Rui ,  Shuo Zhang ,  Genyi Wang ,  Xiaoshe Deng

IPC: H01L21/311 ,  H01L21/3213 ,  H01L29/66 ,  H01L21/321

CPC classification number: H01L21/31116 ,  H01L21/32105 ,  H01L21/32137 ,  H01L29/66325 ,  H01L29/66333

Abstract: Disclosed is a method for removing a polysilicon protection layer (12) on a back face of an IGBT having a field stop structure (10). The method comprises thermally oxidizing the polysilicon protection layer (12) on the back face of the IGBT until the oxidation is terminated on a gate oxide layer (11) located above the polysilicon protection layer (12) to form a silicon dioxide layer (13), and removing the formed silicon dioxide layer (13) and the gate oxide layer (11) by a dry etching process. The method for removing the protection layer is easier to control.

公开(公告)号：US20160372570A1

公开(公告)日：2016-12-22

申请号：US14902205

申请日：2014-06-13

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Xuan Huang ,  Wanli Wang ,  Genyi Wang

IPC: H01L29/66 ,  H01L21/304 ,  H01L29/739 ,  H01L29/08 ,  H01L29/49 ,  H01L23/31 ,  H01L29/10 ,  H01L21/306

CPC classification number: H01L29/66333 ,  H01L21/304 ,  H01L21/30604 ,  H01L21/30625 ,  H01L23/3171 ,  H01L29/0804 ,  H01L29/0834 ,  H01L29/1004 ,  H01L29/1095 ,  H01L29/4916 ,  H01L29/7395

Abstract: A method for manufacturing an IGBT, comprising: providing a substrate having a first surface and a second surface and of a first or second type of electrical conductance; forming grooves at intervals on the first surface of the substrate; filling a semiconductor material of the second or first type of electrical conductance into the grooves to form channels, where the type of electrical conductance of the channels is different from the type of electrical conductance of the substrate; bonding on the first surface of the substrate to form a drift region of the second type of electrical conductance; forming a front-side structure of the IGBT on the basis of the drift region; thinning the substrate starting from the second surface of the substrate until the channels are exposed; and forming a rear-side metal electrode on the channels and the thinned substrate. The method has no specific requirement with respect to sheet flow capacity, nor requires a double-sided exposure machine apparatus, is compatible with a conventional process, and has a simple process and high efficiency.

Abstract translation: 一种制造IGBT的方法，包括：提供具有第一表面和第二表面以及第一或第二类型电导的基板; 在基板的第一表面上间隔地形成槽; 将第二或第一类电导体的半导体材料填充到沟槽中以形成通道，其中通道的导电类型不同于衬底的电导的类型; 在所述衬底的所述第一表面上接合以形成所述第二类型电导的漂移区域; 基于漂移区域形成IGBT的前侧结构; 从衬底的第二表面开始稀释衬底，直到通道暴露; 以及在通道和薄化的基板上形成后侧金属电极。 该方法对于纸张流动能力没有特别要求，也不需要双面曝光机装置，与常规方法兼容，并且具有简单的工艺和高效率。

公开(公告)号：US09443926B2

公开(公告)日：2016-09-13

申请号：US14901606

申请日：2014-06-06

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Shuo Zhang ,  Qiang Rui ,  Xiaoshe Deng ,  Genyi Wang

IPC: H01L29/74 ,  H01L29/06 ,  H01L29/66 ,  H01L29/739 ,  H01L23/528 ,  H01L23/532 ,  H01L23/31

CPC classification number: H01L29/0607 ,  H01L23/3157 ,  H01L23/3171 ,  H01L23/528 ,  H01L23/53219 ,  H01L23/53247 ,  H01L29/0619 ,  H01L29/0834 ,  H01L29/66325 ,  H01L29/66333 ,  H01L29/7393 ,  H01L29/7395

Abstract: A field-stop reverse conducting insulated gate bipolar transistor and a manufacturing method thereof. The transistor comprises a terminal structure (200) and an active region (100). An underlayment of the field-stop reverse conducting insulated gate bipolar transistor is an N-type underlayment, the back surface of the underlayment is provided with an N-type electric field stop layer (1), one surface of the electric field stop layer (1) departing from the underlayment is provided with a back-surface P-type structure (10), and the surface of the back-surface P-type structure (10) is provided with a back-surface metal layer (12). A plurality of polysilicon filling structures (11) which penetrate into the electric field stop layer (1) from the back-surface P-type structure (10) are formed in the active region (100).

Abstract translation: 场阻反向导通绝缘栅双极晶体管及其制造方法。 晶体管包括端子结构（200）和有源区（100）。 场阻反向导通绝缘栅双极晶体管的底层是N型衬垫，衬垫的背面设置有N型电场停止层（1），电场停止层的一个表面 在背衬P型结构（10）的背面设置有背面金属层（12）的背面P型结构（10）的表面。 在有源区（100）中形成有从背面P型结构（10）贯穿电场停止层（1）的多个多晶硅填充结构（11）。

公开(公告)号：US20150155182A1

公开(公告)日：2015-06-04

申请号：US14411978

申请日：2013-07-25

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Qiang Rui ,  Shuo Zhang ,  Genyi Wang ,  Xiaoshe Deng

IPC: H01L21/311 ,  H01L29/66

CPC classification number: H01L21/31116 ,  H01L21/32105 ,  H01L21/32137 ,  H01L29/66325 ,  H01L29/66333

Abstract: Disclosed is a method for removing a polysilicon protection layer (12) on a back face of an IGBT having a field stop structure (10). The method comprises thermally oxidizing the polysilicon protection layer (12) on the back face of the IGBT until the oxidation is terminated on a gate oxide layer (11) located above the polysilicon protection layer (12) to form a silicon dioxide layer (13), and removing the formed silicon dioxide layer (13) and the gate oxide layer (11) by a dry etching process. The method for removing the protection layer is easier to control.

Abstract translation: 公开了一种在具有场停止结构（10）的IGBT的背面上去除多晶硅保护层（12）的方法。 该方法包括在IGBT的背面上热氧化多晶硅保护层（12），直到在位于多晶硅保护层（12）上方的栅极氧化物层（11）上终止氧化以形成二氧化硅层（13） ，并通过干式蚀刻工艺除去形成的二氧化硅层（13）和栅极氧化物层（11）。 去除保护层的方法更容易控制。

公开(公告)号：US10096699B2

公开(公告)日：2018-10-09

申请号：US14392251

申请日：2014-06-05

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Shuo Zhang ,  Qiang Rui ,  Genyi Wang ,  Xiaoshe Deng

IPC: H01L29/73 ,  H01L21/02 ,  H01L29/739 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L21/265 ,  H01L21/28 ,  H01L21/285 ,  H01L21/311 ,  H01L21/324 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49

Abstract: A field-stop reverse conducting insulated gate bipolar transistor and a manufacturing method therefor. The transistor comprises a terminal structure (200) and an active region (100). An underlayment of the field-stop reverse conducting insulated gate bipolar transistor is an N-type underlayment, the back surface of the underlayment is provided with an N-type electric field stop layer (1), one surface of the electric field stop layer departing from the underlayment is provided with a back-surface P-type structure (10), and the surface of the back-surface P-type structure is provided with a back-surface metal layer (12). A plurality of notches (11) which penetrate through the back-surface P-type structure (10) from the back-surface metal layer (12) to the electric field stop layer (1) are formed in the active region (100), and metals of the back-surface metal layer (12) are filled into the notches (11) to form a metal structure which extends into the electric field stop layer (1).

公开(公告)号：US09595520B2

公开(公告)日：2017-03-14

申请号：US14901622

申请日：2014-06-09

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Xiaoshe Deng ,  Shuo Zhang ,  Qiang Rui ,  Genyi Wang

IPC: H01L29/74 ,  H01L27/07 ,  H01L29/66 ,  H01L29/739 ,  H01L29/06 ,  H01L29/08 ,  H01L21/8249 ,  H01L29/868 ,  H01L29/40

CPC classification number: H01L27/0727 ,  H01L21/8249 ,  H01L29/0619 ,  H01L29/0684 ,  H01L29/0834 ,  H01L29/402 ,  H01L29/66333 ,  H01L29/7395 ,  H01L29/868

Abstract: An insulated gate bipolar translator (IGBT) with a built-in diode and a manufacturing method thereof are provided. The IGBT comprises: a semiconductor substrate (1) of the first conduction type which has a first major surface (1S1) and a second major surface (1S2), wherein the semiconductor substrate (1) comprises an active region (100) and a terminal protection area (200) which is located at the outer side of the active region; an insulated gate transistor unit which is formed at the side of the first major surface (1S1) of the active region (100), wherein a channel of the first conduction type is formed thereon during the conduction thereof; and first semiconductor layers (10) of the first conduction type and second semiconductor layers (11) of the second conduction type of the active region, which are formed at the side of the second major surface (1S2) of the semiconductor substrate (1) alternately, wherein the IGBT only comprises the second semiconductor layers (11) in the terminal protection area (200) which is located at the side of the second major surface (1S2) of the semiconductor substrate (1).

Abstract translation: 提供了具有内置二极管的绝缘栅双极转换器（IGBT）及其制造方法。 IGBT包括：具有第一主表面（1S1）和第二主表面（1S2）的第一导电类型的半导体衬底（1），其中半导体衬底（1）包括有源区（100）和端子 保护区域（200），其位于有源区域的外侧; 绝缘栅晶体管单元，其形成在有源区（100）的第一主表面（1S1）侧，其中在其导通期间在其上形成第一导电类型的沟道; 以及形成在半导体衬底（1）的第二主表面（1S2）侧的第一导电类型和第二导电类型的有源区的第二半导体层（11）的第一半导体层（10） 交替地，其中IGBT仅包括端子保护区域（200）中位于半导体衬底（1）的第二主表面（1S2）侧的第二半导体层（11）。

公开(公告)号：US09590029B2

公开(公告)日：2017-03-07

申请号：US14902432

申请日：2014-08-25

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Shengrong Zhong ,  Dongfei Zhou ,  Xiaoshe Deng ,  Genyi Wang

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/739 ,  H01L29/10 ,  H01L29/40 ,  H01L29/16 ,  H01L29/20 ,  H01L29/161 ,  H01L29/04 ,  H01L21/761

CPC classification number: H01L29/0623 ,  H01L21/761 ,  H01L29/045 ,  H01L29/0619 ,  H01L29/1095 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/20 ,  H01L29/401 ,  H01L29/407 ,  H01L29/408 ,  H01L29/66333 ,  H01L29/6634 ,  H01L29/7395 ,  H01L29/7396

Abstract: A method for manufacturing an insulated gate bipolar transistor (100) comprises: providing a substrate (10), forming a field oxide layer (20) on a front surface of the substrate (10), and forming a terminal protection ring (23); performing photoetching and etching on the active region field oxide layer (20) by using an active region photomask, introducing N-type ions into the substrate (10) by using a photoresist as a mask film; depositing and forming a polysilicon gate (31) on the etched substrate (10) of the field oxide layer (20), and forming a protection layer on the polysilicon gate (31); performing junction pushing on an introduction region of the N-type ions, and then forming a carrier enhancement region (41); performing photoetching by using a P well photomask, introducing P-type ions into the carrier enhancement region (41), and performing junction pushing and then forming a P-body region; performing, by means of the polysilicon gate, self-alignment introduction of N-type ions into the P-body region, and performing junction pushing and then forming an N-type heavily doped region; forming sidewalls on two sides of the polysilicon gate, introducing P-type ions into the N-type heavily doped region, and performing junction pushing and then forming a P-type heavily doped region; and removing the protection layer, and then performing introduction and doping of the polysilicon gate. The method reduces a forward voltage drop disposing the carrier enhancement region.

Abstract translation: 一种用于制造绝缘栅双极晶体管（100）的方法，包括：提供衬底（10），在衬底（10）的前表面上形成场氧化物层（20），并形成端子保护环（23）; 通过使用有源区光掩模对有源区域氧化物层（20）进行光刻和蚀刻，通过使用光致抗蚀剂作为掩模膜将N型离子引入到衬底（10）中; 在所述场氧化物层（20）的蚀刻衬底（10）上沉积和形成多晶硅栅极（31），并在所述多晶硅栅极（31）上形成保护层; 在N型离子的导入区域上进行接合，然后形成载流子增强区域（41）。 通过使用P阱光掩模进行光蚀刻，将P型离子引入载体增强区域（41）中，并执行连接推动然后形成P体区域; 通过多晶硅栅极进行N型离子的自对准引入到P体区域中，并进行结压并形成N型重掺杂区域; 在所述多晶硅栅极的两侧形成侧壁，将P型离子引入所述N型重掺杂区域中，并执行结推进，然后形成P型重掺杂区域; 并去除保护层，然后进行多晶硅栅极的引入和掺杂。 该方法减少了设置载流子增强区域的正向压降。

公开(公告)号：US09553164B2

公开(公告)日：2017-01-24

申请号：US14902205

申请日：2014-06-13

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Xuan Huang ,  Wanli Wang ,  Genyi Wang

IPC: H01L21/00 ,  H01L29/66 ,  H01L29/10 ,  H01L21/304 ,  H01L21/306 ,  H01L29/08 ,  H01L29/49 ,  H01L23/31 ,  H01L29/739

CPC classification number: H01L29/66333 ,  H01L21/304 ,  H01L21/30604 ,  H01L21/30625 ,  H01L23/3171 ,  H01L29/0804 ,  H01L29/0834 ,  H01L29/1004 ,  H01L29/1095 ,  H01L29/4916 ,  H01L29/7395

Abstract: A method for manufacturing an IGBT, comprising: providing a substrate having a first surface and a second surface and of a first or second type of electrical conductance; forming grooves at intervals on the first surface of the substrate; filling a semiconductor material of the second or first type of electrical conductance into the grooves to form channels, where the type of electrical conductance of the channels is different from the type of electrical conductance of the substrate; bonding on the first surface of the substrate to form a drift region of the second type of electrical conductance; forming a front-side structure of the IGBT on the basis of the drift region; thinning the substrate starting from the second surface of the substrate until the channels are exposed; and forming a rear-side metal electrode on the channels and the thinned substrate. The method has no specific requirement with respect to sheet flow capacity, nor requires a double-sided exposure machine apparatus, is compatible with a conventional process, and has a simple process and high efficiency.

Abstract translation: 一种制造IGBT的方法，包括：提供具有第一表面和第二表面以及第一或第二类型电导的基板; 在基板的第一表面上间隔地形成槽; 将第二或第一类电导体的半导体材料填充到沟槽中以形成通道，其中通道的导电类型不同于衬底的电导的类型; 在所述衬底的所述第一表面上接合以形成所述第二类型电导的漂移区域; 基于漂移区域形成IGBT的前侧结构; 从衬底的第二表面开始稀释衬底，直到通道暴露; 以及在通道和薄化的基板上形成后侧金属电极。 该方法对于纸张流动能力没有特别要求，也不需要双面曝光机装置，与常规方法兼容，并且具有简单的工艺和高效率。

公开(公告)号：US09502534B2

公开(公告)日：2016-11-22

申请号：US14902294

申请日：2014-09-12

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Shengrong Zhong ,  Genyi Wang ,  Xiaoshe Deng ,  Dongfei Zhou

IPC: H01L29/00 ,  H01L29/66 ,  H01L21/02 ,  H01L29/06 ,  H01L21/311 ,  H01L21/28 ,  H01L21/266 ,  H01L21/027 ,  H01L21/265 ,  H01L21/3213 ,  H01L21/324 ,  H01L21/768 ,  H01L29/167

CPC classification number: H01L29/66666 ,  H01L21/02576 ,  H01L21/0273 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/28035 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32137 ,  H01L21/32139 ,  H01L21/324 ,  H01L21/768 ,  H01L29/0619 ,  H01L29/167 ,  H01L29/6609 ,  H01L29/66712 ,  H01L29/861

Abstract: A preparation method for a power diode, comprising: providing a substrate (10), the substrate (10) having a front surface and a back surface opposite to the front surface, an N-type layer (20) growing on the front surface of the substrate (10), and the N-type layer (20) having a first surface deviating from the substrate (10); forming a terminal protection ring (31, 32, 33); forming an oxide layer (50), and performing knot pushing on the terminal protection ring (31, 32, 33); conducting photoetching using a photoetching plate of an active region and etching the oxidation layer (50) of the active region, and forming a gate oxide layer (60) on the first surface of the N-type layer (20) of the active region; depositing on the gate oxide layer (60) to form a polysilicon layer (70); conducting photoetching using a polysilicon photoetching plate, taking a photoresist (40) as a mask layer to inject P-type ions into the N-type layer (20), and forming a P-type body region (82) beneath the polysilicon layer (70) through ion scattering; forming an N-type heavily doped region; forming a P+region; conducting thermal annealing, activating injected impurities and removing the photoresist (40); and conducting metallization processing on the first surface and the back surface of the substrate (10).

Abstract translation: 一种用于功率二极管的制备方法，包括：提供基板（10），所述基板（10）具有前表面和与所述前表面相对的后表面的N型层（20），所述N型层（20）在 所述基板（10）和具有偏离所述基板（10）的第一表面的所述N型层（20）。 形成端子保护环（31,32,33）; 形成氧化物层（50），并且对所述端子保护环（31,32,33）施加结压力; 使用有源区的光刻板进行光蚀刻，蚀刻有源区的氧化层（50），在有源区的N型层（20）的第一面上形成栅极氧化层（60） 沉积在栅极氧化物层（60）上以形成多晶硅层（70）; 使用多晶硅光刻板进行光蚀刻，以光致抗蚀剂（40）作为掩模层将P型离子注入到N型层（20）中，并在多晶硅层下形成P型体区（82） 70）通过离子散射; 形成N型重掺杂区域; 形成P +区; 进行热退火，激活注入的杂质和去除光致抗蚀剂（40）; 以及在所述基板（10）的所述第一表面和所述背面上进行金属化处理。

公开(公告)号：US09502497B2

公开(公告)日：2016-11-22

申请号：US14902270

申请日：2014-10-22

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Genyi Wang ,  Xiaoshe Deng ,  Shengrong Zong ,  Dongfei Zhou

IPC: H01L29/00 ,  H01L29/06 ,  H01L29/66 ,  H01L21/266 ,  H01L21/265 ,  H01L21/311 ,  H01L21/324 ,  H01L21/027 ,  H01L29/10 ,  H01L21/321 ,  H01L21/3213

CPC classification number: H01L29/0619 ,  H01L21/0273 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/31116 ,  H01L21/32105 ,  H01L21/32137 ,  H01L21/324 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/20 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/41766 ,  H01L29/6606 ,  H01L29/66136 ,  H01L29/66204 ,  H01L29/66325 ,  H01L29/66333 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/7811 ,  H01L29/8611

Abstract: A method for preparing a power diode, including: providing a substrate (10), growing a N type layer (20) on the front surface of the substrate (10); forming a terminal protecting ring; forming an oxide layer (30), knot-pushing to the terminal protecting ring; forming a gate oxide layer (60), depositing a poly-silicon layer (70) on the gate oxide layer (60); depositing a SiO2 layer (80) on the surface of the poly-silicon layer (70) and a oxide layer (50); forming a N type heavy doped region (92); forming a P+ region; removing a photoresist, implanting P type ions using the SiO2 layer (80) as a mask layer, and forming a P type body region; heat annealing; forming a side wall structure in the opening of the poly-silicon layer (70), the gate oxide layer (60) being etched, and removing the SiO2 layer (80); and processing a front surface metallization and a back surface metallization treatment. According to the method for preparing the power diode, by adjusting the isotropy etching level of the SiO2 layer and the ion implanting dose and energy, the threshold voltage of a DMOS structure can be adjusted, and the adjustment of the forward voltage drop for the device can be achieved.

Abstract translation: 一种制备功率二极管的方法，包括：提供衬底（10），在衬底（10）的前表面上生长N型层（20）; 形成端保护环; 形成氧化物层（30），向所述端子保护环打结; 形成栅极氧化物层（60），在所述栅极氧化物层（60）上沉积多晶硅层（70）。 在所述多晶硅层（70）的表面和氧化物层（50）上沉积SiO 2层（80）; 形成N型重掺杂区域（92）; 形成P +区; 去除光致抗蚀剂，使用SiO 2层（80）作为掩模层注入P型离子，形成P型体区; 热退火; 在所述多晶硅层（70）的开口部形成侧壁结构，蚀刻所述栅极氧化物层（60），除去所述SiO 2层（80）。 以及处理前表面金属化和背面金属化处理。 根据制备功率二极管的方法，通过调整SiO2层的各向同性蚀刻水平和离子注入剂量和能量，可以调整DMOS结构的阈值电压，并调整器件的正向压降 可以实现。