公开(公告)号：US07348218B2

公开(公告)日：2008-03-25

申请号：US11467053

申请日：2006-08-24

Applicant: Ching-Yu Ni ,  Tsorng-Dih Yuan ,  Hsin-Yu Pan

Inventor： Ching-Yu Ni ,  Tsorng-Dih Yuan ,  Hsin-Yu Pan

IPC: H01L21/00

CPC classification number: H01L23/433 ,  H01L24/31 ,  H01L2224/16225 ,  H01L2224/27013 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83051 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/1579 ,  H01L2924/16152 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/13111 ,  H01L2924/0665 ,  H01L2224/0401

Abstract: Described are semiconductor package devices with improved reliability and methods of manufacturing thereof. In one embodiment, a package device is disclosed that includes a chip having an active surface and a coupling surface opposite the active surface, where the chip has one or more integrated circuits and bumps. The device also includes a thermal spreader thermally coupled to the coupling surface of the chip for dissipating heat generated by the chip, and a thermal interface material located between the thermal spreader and the coupling surface of the chip for improving the heat dissipation. In addition, the device also includes a boundary material located between the thermal spreader and the coupling surface of the chip, where the boundary material is configured to surround a perimeter of the thermal interface material to maintain the thermal interface material between the thermal spreader and the coupling surface of the chip.

Abstract translation: 描述了具有改进的可靠性的半导体封装器件及其制造方法。 在一个实施例中，公开了一种封装器件，其包括具有有源表面和与有源表面相对的耦合表面的芯片，其中芯片具有一个或多个集成电路和凸块。 该装置还包括热耦合到芯片的耦合表面的散热器，用于散发由芯片产生的热量，以及位于散热器和芯片的耦合表面之间的热界面材料，用于改善散热。 此外，该装置还包括位于散热器和芯片的耦合表面之间的边界材料，其中边界材料构造成围绕热界面材料的周边，以将热界面材料保持在散热器和 耦合表面的芯片。

公开(公告)号：US20090283877A1

公开(公告)日：2009-11-19

申请号：US12466656

申请日：2009-05-15

Applicant: Chia-Lun Tsai ,  Ching-Yu Ni ,  Jack Chen ,  Wen-Cheng Chien

Inventor： Chia-Lun Tsai ,  Ching-Yu Ni ,  Jack Chen ,  Wen-Cheng Chien

IPC: H01L23/552 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L24/11 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/05644 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013

Abstract: A semiconductor device and manufacturing method thereof are disclosed. The device comprises a semiconductor die, a passivation layer, a wiring redistribution layer (RDL), an Ni/Au layer, and a solder mask. The semiconductor die comprises a top metal exposed in an active surface thereof. The passivation layer overlies the active surface of the semiconductor die, and comprises a through passivation opening overlying the top metal. The wiring RDL, comprising an Al layer, overlies the passivation layer, and electrically connects to the top metal via the passivation opening. The solder mask overlies the passivation layer and the wiring RDL, exposing a terminal of the wiring RDL.

Abstract translation: 公开了一种半导体器件及其制造方法。 该器件包括半导体管芯，钝化层，布线再分布层（RDL），Ni / Au层和焊料掩模。 半导体管芯包括在其活性表面中暴露的顶部金属。 钝化层覆盖半导体管芯的有源表面，并且包括覆盖顶部金属的贯通钝化开口。 包括Al层的布线RDL覆盖钝化层，并通过钝化开口电连接到顶部金属。 焊接掩模覆盖钝化层和布线RDL，露出布线RDL的端子。

公开(公告)号：US20070069366A1

公开(公告)日：2007-03-29

申请号：US11237924

申请日：2005-09-29

Applicant: Kuo-Chin Chang ,  Ching-Yu Ni

Inventor： Kuo-Chin Chang ,  Ching-Yu Ni

IPC: H01L23/12

CPC classification number: H01L23/16 ,  H01L23/36 ,  H01L23/562 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/01019 ,  H01L2924/15311

Abstract: A constraint stiffener for reinforcing an integrated circuit package is provided. In one embodiment, the constraint stiffener comprises a rigid, planar base element for bonding to an integrated circuit substrate. The base element has a plurality of elongated support members, and the base element has an opening therein for surrounding an integrated circuit. The base element and support members reduce warpage due to thermal expansion mismatches between at least the integrated circuit and the substrate. In one embodiment, the elongated support members are detachable from the corners of the base element. In another embodiment, the elongated support members have means for attaching and detaching to the corners of the base element. In yet another embodiment, the elongated support members are detachable from about the midsections of the base element. In another embodiment, the elongated support members have means for attaching and detaching to the midsections of the base element.

Abstract translation: 提供了用于加强集成电路封装的约束加强件。 在一个实施例中，约束加强件包括用于结合到集成电路基板的刚性平面基座元件。 基座元件具有多个细长的支撑构件，并且基座元件具有用于围绕集成电路的开口。 基部元件和支撑构件由于至少集成电路和基板之间的热膨胀失配而减少翘曲。 在一个实施例中，细长支撑构件可从基座元件的角部拆卸。 在另一个实施例中，细长支撑构件具有用于附接和分离到基部元件的角部的装置。 在另一个实施例中，细长的支撑构件可从基部元件的中央部分的周围拆卸。 在另一个实施例中，细长的支撑构件具有用于附接和分离到基部元件的中部的装置。

公开(公告)号：US20060261469A1

公开(公告)日：2006-11-23

申请号：US11134303

申请日：2005-05-23

Applicant: Ching-Yu Ni ,  Hsin-Yu Pan ,  Tsorng Yuan

Inventor： Ching-Yu Ni ,  Hsin-Yu Pan ,  Tsorng Yuan

IPC: H01L23/34 ,  H01L21/50

CPC classification number: H01L23/433 ,  H01L23/373 ,  H01L23/3737 ,  H01L24/29 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/0401

Abstract: A semiconductor package having a sealing membrane for thermal interface material is provided. In one embodiment, the semiconductor package comprises a semiconductor die, a heat spreader, and a sealed membrane for containing a thermal interface material (TIM) therein, the sealed membrane is located between the die and the heat spreader for transmitting heat generated from the die to the heat spreader.

Abstract translation: 提供一种具有用于热界面材料的密封膜的半导体封装。 在一个实施例中，半导体封装包括半导体管芯，散热器和用于在其中容纳热界面材料（TIM）的密封膜，密封膜位于管芯和散热器之间，用于传递从管芯产生的热量 到散热器。

公开(公告)号：US08766400B2

公开(公告)日：2014-07-01

申请号：US12843869

申请日：2010-07-26

Applicant: Ching-Yu Ni

Inventor： Ching-Yu Ni

IPC: H01L23/52

CPC classification number: H01L28/60 ,  H01F17/0013 ,  H01F41/041 ,  H01L27/12 ,  H01L28/10

Abstract: An electronic device and fabrication method thereof are provided. The electronic device contains a glass substrate, a patterned semiconductor substrate, having at least one opening, disposed on the glass substrate and at least one passive component having a first conductive layer and a second conductive layer, wherein the first conductive layer is disposed between the patterned semiconductor substrate and the glass substrate.

Abstract translation: 提供了一种电子设备及其制造方法。 该电子装置包括玻璃基板，具有至少一个开口的图案化半导体基板，设置在玻璃基板上，以及至少一个无源部件，具有第一导电层和第二导电层，其中第一导电层设置在 图案化的半导体衬底和玻璃衬底。

公开(公告)号：US08384222B2

公开(公告)日：2013-02-26

申请号：US13030887

申请日：2011-02-18

Applicant: Chia-Lun Tsai ,  Ching-Yu Ni ,  Jack Chen ,  Wen-Cheng Chien

Inventor： Chia-Lun Tsai ,  Ching-Yu Ni ,  Jack Chen ,  Wen-Cheng Chien

IPC: H01L23/48

CPC classification number: H01L24/11 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/05644 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013

Abstract: A semiconductor device and manufacturing method thereof are disclosed. The device comprises a semiconductor die, a passivation layer, a wiring redistribution layer (RDL), an Ni/Au layer, and a solder mask. The semiconductor die comprises a top metal exposed in an active surface thereof. The passivation layer overlies the active surface of the semiconductor die, and comprises a through passivation opening overlying the top metal. The wiring RDL, comprising an Al layer, overlies the passivation layer, and electrically connects to the top metal via the passivation opening. The solder mask overlies the passivation layer and the wiring RDL, exposing a terminal of the wiring RDL.

Abstract translation: 公开了一种半导体器件及其制造方法。 该器件包括半导体管芯，钝化层，布线再分布层（RDL），Ni / Au层和焊料掩模。 半导体管芯包括在其活性表面中暴露的顶部金属。 钝化层覆盖半导体管芯的有源表面，并且包括覆盖顶部金属的贯通钝化开口。 包括Al层的布线RDL覆盖钝化层，并通过钝化开口电连接到顶部金属。 焊接掩模覆盖钝化层和布线RDL，露出布线RDL的端子。

公开(公告)号：US08367477B2

公开(公告)日：2013-02-05

申请号：US12722486

申请日：2010-03-11

Applicant: Wen-Cheng Chien ,  Ching-Yu Ni ,  Shu-Ming Chang

Inventor： Wen-Cheng Chien ,  Ching-Yu Ni ,  Shu-Ming Chang

IPC: H01L23/48

CPC classification number: B05D1/36 ,  B81B2207/096 ,  B81C1/00301 ,  H01L21/56 ,  H01L21/6835 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L27/14618 ,  H01L31/02002 ,  H01L31/0203 ,  H01L33/486 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/01078 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/00

Abstract: An embodiment of the invention provides a method for forming an electronic device package, which includes providing a carrier substrate having an upper surface and an opposite lower surface; forming a cavity from the upper surface of the carrier substrate; disposing an electronic device having a conducting electrode in the cavity; forming a filling layer in the cavity, wherein the filling layer surround the electronic device; thinning the carrier substrate from the lower surface to a predetermined thickness; forming at least a through-hole in the electronic device or the in the carrier substrate; and forming a conducting layer over a sidewall of the through-hole, wherein the conducting layer electrically connects to the conducting electrode.

公开(公告)号：US20110140267A1

公开(公告)日：2011-06-16

申请号：US12849089

申请日：2010-08-03

Applicant: Chia-Lun TSAI ,  Ching-Yu Ni ,  Tien-Hao Huang ,  Chia-Ming Cheng ,  Wen-Cheng Chien ,  Nan-Chun Lin ,  Wei-Ming Chen ,  Shu-Ming Chang ,  Bai-Yao Lou

Inventor： Chia-Lun TSAI ,  Ching-Yu Ni ,  Tien-Hao Huang ,  Chia-Ming Cheng ,  Wen-Cheng Chien ,  Nan-Chun Lin ,  Wei-Ming Chen ,  Shu-Ming Chang ,  Bai-Yao Lou

IPC: H01L23/498 ,  H01L21/60

CPC classification number: H01L24/20 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5389 ,  H01L23/544 ,  H01L24/19 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2223/54486 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/83132 ,  H01L2224/92 ,  H01L2224/92244 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01021 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15184 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00

Abstract: The invention provides an electronic device package and a method for fabricating the same. The electronic device package includes a carrier wafer. An electronic device chip with a plurality of conductive pads thereon is disposed over the carrier wafer. An isolation laminating layer includes a lower first isolation layer, which covers the carrier wafer and the electronic device chip, and an upper second isolation layer. The isolation laminating layer has a plurality of openings to expose the conductive pads. A plurality of redistribution patterns is conformably formed on the isolation laminating layer and in the openings. The redistribution patterns are electrically connected to the conductive pads, respectively. A plurality of conductive bumps is respectively formed on the redistribution patterns, electrically connected to the conductive pads.

Abstract translation: 本发明提供一种电子器件封装及其制造方法。 电子器件封装包括载体晶片。 具有多个导电焊盘的电子器件芯片设置在载体晶片上。 隔离层压层包括覆盖载体晶片和电子器件芯片的下部第一隔离层和上部第二隔离层。 隔离层压层具有多个开口以露出导电垫。 在隔离层压层和开口中顺应地形成多个再分配图案。 再分布图案分别电连接到导电焊盘。 多个导电凸块分别形成在再分布图案上，电连接到导电焊盘。

公开(公告)号：US20090289273A1

公开(公告)日：2009-11-26

申请号：US12471255

申请日：2009-05-22

Applicant: Chia-Lun Tsai ,  Ching-Yu Ni ,  Wen-Cheng Chien ,  Shang-Yi Wu ,  Cheng-Te Chou

Inventor： Chia-Lun Tsai ,  Ching-Yu Ni ,  Wen-Cheng Chien ,  Shang-Yi Wu ,  Cheng-Te Chou

IPC: H01L33/00

CPC classification number: H01L33/385 ,  H01L33/62 ,  H01L33/64 ,  H01L33/642 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A light emitting device package structure is described. The light emitting device package structure includes a substrate serving as a carrier supporting a light emitting device chip. The substrate and the light emitting device chip have a chip side and a substrate side separately. A first electrode layer is disposed on a first surface of the light emitting device chip and a second electrode layer is disposed on a second surface of the light emitting device chip, in which the first surface and the second surface are not coplanar. A first conductive trace is electrically connected to the first electrode layer and a second conductive trace is electrically connected to the second electrode layer. At least the first conductive trace or the second conductive trace is formed along the chip side and the substrate side simultaneously.

Abstract translation: 描述了发光器件封装结构。 发光器件封装结构包括用作支撑发光器件芯片的载体的衬底。 基板和发光元件芯片分别具有芯片侧和基板侧。 第一电极层设置在发光器件芯片的第一表面上，并且第二电极层设置在发光器件芯片的第二表面上，其中第一表面和第二表面不是共面的。 第一导电迹线电连接到第一电极层，并且第二导电迹线电连接到第二电极层。 至少第一导电迹线或第二导电迹线同时沿着芯片侧和衬底侧形成。

公开(公告)号：US20060286719A1

公开(公告)日：2006-12-21

申请号：US11467053

申请日：2006-08-24

Applicant: Ching-Yu Ni ,  Tsorng-Dih Yuan ,  Hsin-Yu Pan

Inventor： Ching-Yu Ni ,  Tsorng-Dih Yuan ,  Hsin-Yu Pan

IPC: H01L21/00

CPC classification number: H01L23/433 ,  H01L24/31 ,  H01L2224/16225 ,  H01L2224/27013 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83051 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/1579 ,  H01L2924/16152 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/13111 ,  H01L2924/0665 ,  H01L2224/0401

Abstract: Described are semiconductor package devices with improved reliability and methods of manufacturing thereof. In one embodiment, a package device is disclosed that includes a chip having an active surface and a coupling surface opposite the active surface, where the chip has one or more integrated circuits and bumps. The device also includes a thermal spreader thermally coupled to the coupling surface of the chip for dissipating heat generated by the chip, and a thermal interface material located between the thermal spreader and the coupling surface of the chip for improving the heat dissipation. In addition, the device also includes a boundary material located between the thermal spreader and the coupling surface of the chip, where the boundary material is configured to surround a perimeter of the thermal interface material to maintain the thermal interface material between the thermal spreader and the coupling surface of the chip.

Abstract translation: 描述了具有改进的可靠性的半导体封装器件及其制造方法。 在一个实施例中，公开了一种封装器件，其包括具有有源表面和与有源表面相对的耦合表面的芯片，其中芯片具有一个或多个集成电路和凸块。 该装置还包括热耦合到芯片的耦合表面的散热器，用于散发由芯片产生的热量，以及位于散热器和芯片的耦合表面之间的热界面材料，用于改善散热。 此外，该装置还包括位于散热器和芯片的耦合表面之间的边界材料，其中边界材料构造成围绕热界面材料的周边，以将热界面材料保持在散热器和 耦合表面的芯片。