Apparatus and methods for transferring charge

    公开(公告)号:US12266961B2

    公开(公告)日:2025-04-01

    申请号:US17824687

    申请日:2022-05-25

    Abstract: Apparatus for delivering power from a battery node of a battery to an output node, the output node coupled to an analyte monitoring device, the apparatus comprising: a slow charging path between the battery node and the output node; a fast charging path parallel to the slow charging path, the fast charging path switchably coupled between the battery node and the output node; and control circuitry configured to: selectively couple the fast charging path between the battery node and the output node to allow faster transfer of charge between the battery node and the output node than the slow charging path.

    Driver circuitry
    13.
    发明授权

    公开(公告)号:US11958075B2

    公开(公告)日:2024-04-16

    申请号:US17092613

    申请日:2020-11-09

    CPC classification number: B06B1/0223 B06B1/06 H03K17/30 B06B2201/55

    Abstract: The present disclosure relates to circuitry for driving a load. The circuitry comprises driver circuitry configured to generate a drive signal, based on an input signal to the driver circuitry, for driving the load, and commutator circuitry for coupling the driver circuitry to the load. The commutator circuitry is configured to alternate between commutation states in response to a level of the drive signal meeting a drive signal threshold or in response to a level of the input signal meeting a first input signal threshold. The circuitry is configured to apply an offset to the input signal when the input signal is below a second input signal threshold so as to increase a minimum level of the drive signal above the drive signal threshold or to increase a minimum level of the input signal above the first input signal threshold.

    Circuitry for analyte measurement
    14.
    发明授权

    公开(公告)号:US11846600B2

    公开(公告)日:2023-12-19

    申请号:US17463796

    申请日:2021-09-01

    CPC classification number: G01N27/3273 G01R19/165 G01R19/16566

    Abstract: Circuitry for measuring a characteristic of an electrochemical cell, the circuitry comprising: a comparator having a first comparator input, a second comparator input and a comparator output; a feedback path between the comparator output and the second comparator input configured to provide a feedback signal to the second comparator input; and a loop filter configured to apply filtering to the feedback path to generate the feedback signal, wherein the loop filter comprises the electrochemical cell.

    Detection of live speech
    15.
    发明授权

    公开(公告)号:US11705109B2

    公开(公告)日:2023-07-18

    申请号:US17091316

    申请日:2020-11-06

    CPC classification number: G10L15/06 G10L19/26 G10L25/78 G10L2025/937

    Abstract: A method of detecting live speech comprises: receiving a signal containing speech; obtaining a first component of the received signal in a first frequency band, wherein the first frequency band includes audio frequencies; and obtaining a second component of the received signal in a second frequency band higher than the first frequency band. Then, modulation of the first component of the received signal is detected; modulation of the second component of the received signal is detected; and the modulation of the first component of the received signal and the modulation of the second component of the received signal are compared. It may then be determined that the speech may not be live speech, if the modulation of the first component of the received signal differs from the modulation of the second component of the received signal.

    Time encoding modulator circuitry
    16.
    发明授权

    公开(公告)号:US11509272B2

    公开(公告)日:2022-11-22

    申请号:US17319620

    申请日:2021-05-13

    Abstract: This application describes time-encoding modulator circuitry (200), and in particular a PWM modulator suitable for use for a class-D amplifier. A forward signal path receives a digital input signal (Din) and outputs an output PWM signal (Sout) and includes a first PWM modulator (101). A feedback path provides feedback to an input of the first PWM modulator (101). The feedback path includes an ADC (203) which receive a first PWM signal (Sa) derived from the output PWM signal. The ADC (203) includes a second PWM modulator (401) which generates a second PWM signal (Sb) based on the first PWM signal. A controller (201) controls the second PWM modulator such that a PWM carrier of the second PWM signal is phase and frequency matched to a PWM carrier of the output PWM signal.

    Class-D amplifier circuits
    17.
    发明授权

    公开(公告)号:US10171049B2

    公开(公告)日:2019-01-01

    申请号:US15726584

    申请日:2017-10-06

    Abstract: Methods and apparatus for Class-D amplifier circuits with improved power efficiency. The circuit has an output stage with at least first and second switches and a modulator that receives an input signal to be amplified, SIN, and a first clock signal fSW. The modulator controls the duty cycles of the first and second switches, within a switching cycle based on the input signal, wherein the switching cycle has a switching frequency based on the first clock signal. A frequency controller controls the frequency of the first clock signal in response to an indication of the amplitude of the input signal so as to provide a first switching frequency at a first input signal amplitude and a second, lower, switching frequency at a second, lower, input signal amplitude. A lower switching frequency can be tolerated at low signal amplitudes and varying the switching frequency in this way thus maintains stability whilst reducing switching power losses.

    Class-D amplifier circuits
    18.
    发明授权

    公开(公告)号:US09787261B2

    公开(公告)日:2017-10-10

    申请号:US15278862

    申请日:2016-09-28

    Abstract: Methods and apparatus for Class-D amplifier circuits with improved power efficiency. The circuit has an output stage with at least first and second switches and a modulator that receives an input signal to be amplified, SIN, and a first clock signal fSW. The modulator controls the duty cycles of the first and second switches, within a switching cycle based on the input signal, wherein the switching cycle has a switching frequency based on the first clock signal. A frequency controller controls the frequency of the first clock signal in response to an indication of the amplitude of the input signal so as to provide a first switching frequency at a first input signal amplitude and a second, lower, switching frequency at a second, lower, input signal amplitude. A lower switching frequency can be tolerated at low signal amplitudes and varying the switching frequency in this way thus maintains stability while reducing switching power losses.

    Computing circuitry
    19.
    发明授权

    公开(公告)号:US11783171B2

    公开(公告)日:2023-10-10

    申请号:US16554984

    申请日:2019-08-29

    CPC classification number: G06N3/065 H03M1/745

    Abstract: This application relates to computing circuitry (200, 500, 600) for analogue computing. A plurality of current generators (201) are each configured to generate a defined current (ID1, ID2, . . . IDj) based on a respective input data value (D1, D2, . . . Dj). A memory array (202), having at least one set (204) of programmable-resistance memory cells (203), is arranged to receive the defined currents from each of the current generators at a respective signal line (206). Each set (204) of programmable-resistance memory cells (203) includes a memory cell associated with each signal line that, in use, can be connected between the relevant signal line and a reference voltage so as to generate a voltage on the signal line. An adder module (207) is coupled to each of the signal lines to generate a voltage at an output node (210) based on the sum of the voltages on each of the signal lines.

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