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公开(公告)号：US20190324060A1
公开(公告)日：2019-10-24
申请号：US15956567
申请日：2018-04-18
Applicant: Dell Products L.P.
Inventor： Vasa Mallikarjun Goud , Bhyrav M. Mutnury , Umesh Chandra
IPC: G01R13/22
Abstract: An oscilloscope system includes a chassis with an input signal port and a display system located on the chassis that are both coupled to a measurement engine. The measurement engine captures, via an input signal probe that is coupled to the input signal port and a device under test, a first output test pattern that is generated by the device under test in response to a first input test pattern that is received from a transmitter device. The measurement engine derives, using the first input test pattern, a transfer function for the device under test. The measurement engine captures a second input test pattern that is received from the transmitter device and that is different than the first input test pattern and mathematically convolutes, using the second input test pattern, the transfer function for the device under test to generate a reference measurement.
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公开(公告)号：US20190273341A1
公开(公告)日：2019-09-05
申请号：US15909802
申请日：2018-03-01
Applicant: Dell Products L.P.
Inventor： Umesh Chandra , Sandor Farkas , Bhyrav M. Mutnury
IPC: H01R13/646 , H01R12/71 , H01R13/26 , H01R13/03
Abstract: In accordance with some embodiments of the present disclosure, a connector may include a housing and a pin housed in the housing and configured to electrically couple to a corresponding electrically-conductive conduit of a device comprising the connector. A body of the pin is formed of a material having a first conductivity. The pin may include a first portion between a proximal point of the pin and a medial point of the pin, and a second portion between the medial point of the pin and a distal point of the pin. The medial point of the pin is proximate to a point of electrical contact of the pin with another pin. The second portion is at least partially covered by a layer of material having a second conductivity that is lower than the first conductivity.
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公开(公告)号：US10103910B1
公开(公告)日：2018-10-16
申请号：US15903978
申请日：2018-02-23
Applicant: Dell Products L.P.
Inventor： Umesh Chandra , Bhyrav M. Mutnury , Arun Reddy Chada , Han Deng
Abstract: A PAM equalization optimization system includes a BIOS coupled to a PAM engine and an equalization engine. The BIOS determines an effective equalization tap number of equalization taps that each provide an equalization result above a predetermined amount. The BIOS then determines whether the effective equalization tap number is greater than a predetermined fraction of an available equalization tap number of equalization taps that are available for equalizing a signal. When the effective equalization tap number is greater than the predetermined fraction of the available equalization tap number, the BIOS causes the equalization engine to perform per-symbol equalization on signals modulated using the PAM engine. When the effective equalization tap number is not greater than the predetermined fraction of the available equalization tap number, the BIOS causes the equalization engine to perform per-bit equalization on signals modulated using the PAM engine.
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公开(公告)号：US20160266204A1
公开(公告)日：2016-09-15
申请号：US14644867
申请日：2015-03-11
Applicant: Dell Products L.P.
Inventor： Umesh Chandra , Timothy Thinh Mai
IPC: G01R31/317 , G01R31/3181
CPC classification number: G01R31/31703 , G01R31/31708 , G01R31/31712 , G01R31/31716 , G01R31/3177 , G01R31/31813 , G01R31/31907 , G06F11/2221
Abstract: A backplane testing system includes a test backplane coupled to a test device chassis and including a first connector system, a second connector system, and channels that connect the first connector system and the second connector system. A first test device in a first test device slot on the test device chassis engages the first connector system and provides a loop back circuit for the first connector system. A second test device in a second test device slot on the test device chassis engages the second connector system. The second test device sends a test signal through a channel on the test backplane such that the test signal is provided to the loop back circuit on the first test device and received back through the channel. The second test device analyzes the test signal that is received to determine a testing compliance of the channel on the test backplane.
Abstract translation: 背板测试系统包括耦合到测试设备机箱并包括第一连接器系统，第二连接器系统和连接第一连接器系统和第二连接器系统的通道的测试背板。 测试设备底盘上的第一测试设备插槽中的第一测试设备接合第一连接器系统，并为第一连接器系统提供环回电路。 第二测试设备在测试设备底盘上的第二测试设备插槽中接合第二连接器系统。 第二测试设备通过测试背板上的通道发送测试信号，使得测试信号被提供给第一测试设备上的环回电路并通过通道接收回来。 第二个测试设备分析接收到的测试信号，以确定测试背板上的通道的测试符合性。
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公开(公告)号：US11882655B2
公开(公告)日：2024-01-23
申请号：US16888644
申请日：2020-05-29
Applicant: DELL PRODUCTS L.P.
Inventor： Umesh Chandra , Douglas Wallace , Bhyrav Mutnury
CPC classification number: H05K1/111 , H05K1/025 , H05K1/0215 , H05K2201/10318 , H05K2201/10636
Abstract: A high-speed transmission circuit comprises, as part of a signal path, a connector pin disposed on a pad that comprises an unused pad region. The unused pad region is not considered part of the signal path but is part of a resonant sub-circuit. In various embodiments, by properly adjusting the dimensions of the pad region and other structures in the high-speed transmission circuit, resonant frequencies of the sub-circuit are shifted to a frequency range that is outside of the frequency range of interest in the signal path, thereby, reducing insertion loss and increasing signal integrity without compromising mechanical stability.
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Patent Agency Ranking
公开(公告)号：US11747295B2
公开(公告)日：2023-09-05
申请号：US17451266
申请日：2021-10-18
Applicant: Dell Products L.P.
Inventor： Bhyrav Mutnury , Umesh Chandra
CPC classification number: G01N27/223 , G01N27/221 , G06F11/3024 , G06F11/3058 , G08B21/182
Abstract: In one or more embodiments, one or more systems, one or more methods, and/or one or more processes may measure at least one of a first height value and a first width value of a first eye diagram of a first signal; measure at least one of a second height value and a second width value of a second eye diagram of a second signal; determine at least one of a height difference value and a width difference value respectively between the at least one of the first height value and the first width value of the first eye diagram and the at least one of the second height value and the second width value of the second eye diagram; and determine that the at least one of the height difference value and the width difference value respectively meets or exceeds a height threshold value or a width threshold value.
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公开(公告)号：US20230119282A1
公开(公告)日：2023-04-20
申请号：US17451266
申请日：2021-10-18
Applicant: Dell Products L.P.
Inventor： Bhyrav Mutnury , Umesh Chandra
Abstract: In one or more embodiments, one or more systems, one or more methods, and/or one or more processes may measure at least one of a first height value and a first width value of a first eye diagram of a first signal; measure at least one of a second height value and a second width value of a second eye diagram of a second signal; determine at least one of a height difference value and a width difference value respectively between the at least one of the first height value and the first width value of the first eye diagram and the at least one of the second height value and the second width value of the second eye diagram; and determine that the at least one of the height difference value and the width difference value respectively meets or exceeds a height threshold value or a width threshold value.
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公开(公告)号：US11445599B2
公开(公告)日：2022-09-13
申请号：US16998977
申请日：2020-08-20
Applicant: DELL PRODUCTS L.P.
Inventor： Umesh Chandra , Bhyrav M. Mutnury
Abstract: A multi-layer PCB has conductive vias (134) passing through multiple layers. A layer may have a conductive non-functional feature (710) physically contacting a via but not surrounding the via, to make the PCB more resistant to thermal stresses while, at the same time, reducing the parasitic capacitance compared to a prior art non-functional pad (310n).
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公开(公告)号：US11102878B1
公开(公告)日：2021-08-24
申请号：US17061483
申请日：2020-10-01
Applicant: DELL PRODUCTS L.P.
Inventor： Umesh Chandra
Abstract: A high-speed transmission circuit design reduces or eliminates the presence of unwanted stub-effects and avoids uncontrolled line impedances that in existing circuits cause impedance mismatches that give rise to unwanted reflections and, ultimately, degrade signal integrity, e.g., in belly-to-belly configurations involving Quad Small Form-Factor Pluggable Double Density (QSFP DD) connectors. In various embodiments, by preventing overcrowding of signal lines, the circuit design further reduces crosstalk and increases signal integrity.
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公开(公告)号：US11026321B2
公开(公告)日：2021-06-01
申请号：US16264939
申请日：2019-02-01
Applicant: Dell Products L.P.
Inventor： Umesh Chandra , Chun-Lin Liao , Bhyrav M. Mutnury
Abstract: A differential trace pair system includes a board including a board structure having a first, a second, a third, and a fourth board structure member, wherein a distance between the first and the third board structure members is longer than a distance between the second and the fourth board structure members. The differential trace pair system further includes a differential trace pair that includes a first differential trace extending between the first and the third board structure members and a second differential trace extending between the second and the fourth board structure members. The second differential trace having a serpentine structure that includes a first portion that continuously transitions away from the first differential trace and a second portion that is contiguous with the first portion, the second portion continuously transitions towards the first differential trace.
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