公开(公告)号：US10053359B2

公开(公告)日：2018-08-21

申请号：US15298657

申请日：2016-10-20

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Philip H. Bowles ,  Stephen R. Hooper

IPC: B81B7/02

CPC classification number: B81B7/02 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2207/07 ,  B81B2207/09

Abstract: Microelectronic packages and methods for producing microelectronic packages are provided. In one embodiment, the method includes bonding a first Microelectromechanical Systems (MEMS) die having a first MEMS transducer structure thereon to a cap piece. The first MEMS die and cap piece are bonded such that a first hermetically-sealed cavity is formed enclosing the first MEMS transducer. A second MEMS die having a second MEMS transducer structure thereon is further bonded to one of the cap piece and the second MEMS die. The second MEMS die and the cap piece are bonded such that a second hermetically-sealed cavity is formed enclosing the second MEMS transducer. The second hermetically-sealed cavity contains a different internal pressure than does the first hermetically-sealed cavity.

公开(公告)号：US20170084519A1

公开(公告)日：2017-03-23

申请号：US14861543

申请日：2015-09-22

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： THOMAS C. SPEIGHT ,  Stephen R. Hooper

IPC: H01L23/495 ,  H01L21/78 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/49541 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/49861 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/97 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A semiconductor die is electrically connected to the leads of a flagless lead frame and is fully encapsulated by encapsulant to form a semiconductor package. A method of manufacturing the semiconductor package entails encapsulating a flagless lead frame with a first encapsulant such that a top surface of the leads of the flagless lead frame are exposed from the first encapsulant. A semiconductor die is mounted directly to the first encapsulant located in a central region of the lead frame. Electrically conductive interconnects are formed between die pads on the semiconductor die and the top surface of respective leads of the lead frame. The semiconductor die, conductive interconnects, and top surface of the leads is encapsulated with a second encapsulant so that the semiconductor die is sandwiched between the first and second encapsulants, thus isolating the semiconductor die from package stresses.

公开(公告)号：US09455216B2

公开(公告)日：2016-09-27

申请号：US14696917

申请日：2015-04-27

Applicant: Freescale Semiconductor, Inc.

Inventor： Dwight L. Daniels ,  Stephen R. Hooper ,  Alan J. Magnus ,  Justin E. Poarch

IPC: H01L23/495 ,  H01L23/00 ,  H01L21/48 ,  H01L23/31

CPC classification number: H01L23/49537 ,  H01L21/4842 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49558 ,  H01L23/49586 ,  H01L24/97 ,  H01L2924/181 ,  Y10T29/49121 ,  H01L2924/00

Abstract: A structure to improve saw singulation quality and wettability of integrated circuit packages (140) is assembled with lead frames (112) having half-etched recesses (134) in leads. In one embodiment, the structure is a lead frame strip (110) having a plurality of lead frames. Each of the lead frames includes a depression (130) that is at least partially filled with a material (400) prior to singulating the lead frame strip. In another embodiment, the structure is a semiconductor device package (140) that includes a semiconductor device encapsulated in a package body (142) having a plurality of leads (120). Each lead has an exposed portion external to the package. There is recess (134) at a corner of each lead. Each recess has a generally concave configuration. Each recess is filled with a removable material (300).

Abstract translation: 用于提高集成电路封装（140）的锯切质量和润湿性的结构与在引线中具有半蚀刻凹槽（134）的引线框架（112）组装在一起。 在一个实施例中，该结构是具有多个引线框架的引线框架条（110）。 每个引线框架包括在分割引线框架条之前至少部分地填充有材料（400）的凹陷（130）。 在另一个实施例中，该结构是半导体器件封装（140），其包括封装在具有多个引线（120）的封装主体（142）中的半导体器件。 每个引线在封装外部具有暴露部分。 在每个引线的拐角处有凹槽（134）。 每个凹部具有大致凹形的构造。 每个凹部填充有可移除材料（300）。