公开(公告)号：US09035679B2

公开(公告)日：2015-05-19

申请号：US13886423

申请日：2013-05-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei Yuan ,  Mahbub Rashed ,  Irene Yuh-Ling Lin ,  Jongwook Kye

IPC: G06F17/50 ,  H01L23/522 ,  H01L27/02 ,  H01L27/118 ,  H01L23/528

CPC classification number: G06F17/5077 ,  H01L23/5221 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments described herein provide approaches for improving a standard cell connection for circuit routing. Specifically, provided is an IC device having a plurality of cells, a first metal layer (M1) pin coupled to a contact bar extending from a first cell of the plurality of cells, and a second metal layer (M2) wire coupled to the contact bar, wherein the contact bar extends across at least one power rail. By extending the contact bar into an open area between the plurality of cells to couple the M1 pin and the M2 wire, routing efficiency and chip scaling are improved.

Abstract translation: 本文描述的实施例提供了用于改进电路布线的标准单元连接的方法。 具体地，提供有具有多个单元的IC器件，耦合到从多个单元的第一单元延伸的接触棒的第一金属层（M1）引脚和耦合到该触点的第二金属层（M2）线 杆，其中接触杆延伸穿过至少一个电源轨。 通过将接触杆延伸到多个单电池之间的开放区域中以耦合M1引脚和M2线，提高了布线效率和芯片缩放。

公开(公告)号：US20140258960A1

公开(公告)日：2014-09-11

申请号：US13792946

申请日：2013-03-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Navneet Jain ,  Yunfei Deng ,  Mahbub Rashed ,  David Doman ,  Qi Xiang ,  Jongwook Kye

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  Y02T10/82

Abstract: An approach and apparatus are provided for optimizing and combining different semiconductor technologies into a single graphic data system. Embodiments include generating a planar semiconductor layout design, generating a three-dimensional (e.g., FinFET) semiconductor layout design, and combining the planar design and the FinFET design in a common graphic data system.

Abstract translation: 提供了将不同半导体技术优化并组合成单个图形数据系统的方法和装置。 实施例包括生成平面半导体布局设计，产生三维（例如，FinFET）半导体布局设计，以及将平面设计和FinFET设计组合在通用图形数据系统中。

公开(公告)号：US20190206717A1

公开(公告)日：2019-07-04

申请号：US15861799

申请日：2018-01-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xuelian Zhu ,  Jia Zeng ,  Chenchen Wang ,  Jongwook Kye

IPC: H01L21/768 ,  H01L21/48

CPC classification number: H01L21/768 ,  H01L21/4857

Abstract: Methods of patterning metallization lines having variable widths in a metallization layer. A first mandrel layer is formed over a mask layer, with the mask layer overlying a second mandrel layer. The first mandrel layer is etched to form mandrel lines that have variable widths. The first non-mandrel trenches are etched in the mask layer, where the non-mandrel trenches have variable widths. The first mandrel lines are used to etch mandrel trenches in the mask layer, so that the mandrel lines and first non-mandrel lines define a mandrel pattern. The second mandrel layer is etched according to the mandrel pattern to form second mandrel lines, with the second mandrel lines having the variable widths of the plurality of first mandrel lines and the variable widths of the plurality of non-mandrel trenches.

公开(公告)号：US20170263506A1

公开(公告)日：2017-09-14

申请号：US15067953

申请日：2016-03-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Guillaume Bouche ,  Tuhin Guha Neogi ,  Andy Chi-Hung Wei ,  Jia Zeng ,  Jongwook Kye ,  Jason Eugene Stephens ,  Irene Yuh-Ling Lin ,  Sudharshanan Raghunathan ,  Lei Yuan

IPC: H01L21/8238 ,  H01L21/768 ,  G06F17/50 ,  H01L21/027 ,  H01L27/092 ,  H01L23/535 ,  H01L21/8234 ,  H01L21/285

CPC classification number: H01L21/823871 ,  G06F17/5072 ,  H01L21/027 ,  H01L21/28518 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823821 ,  H01L23/535 ,  H01L27/0886 ,  H01L27/0924

Abstract: At least one method, apparatus and system disclosed herein for forming a finFET device having a pass-through structure. A first gate structure and a second gate structure are formed on a semiconductor wafer. A first active area is formed on one end of the first and second gate structures. A second active area is formed on the other end of the first and second gate structures. A trench silicide (TS) structure self-aligned to the first and second gate structures is formed. The TS structure is configured to operatively couple the first active area to the second active area.

公开(公告)号：US09679809B1

公开(公告)日：2017-06-13

申请号：US15077564

申请日：2016-03-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jongwook Kye ,  Yan Wang ,  Chenchen Wang ,  Wenhui Wang ,  Lei Yuan ,  Jia Zeng ,  Guillaume Bouche

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/28 ,  H01L45/00

CPC classification number: H01L21/28141 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76816 ,  H01L45/1691

Abstract: A method of forming a pattern for interconnect lines in an integrated circuit includes providing a structure having a first lithographic stack, a mandrel layer and a pattern layer disposed over a dielectric stack. Patterning the structure to form mandrels in the mandrel layer and disposing a spacer layer over the mandrels. Etching the spacer layer to form spacers disposed on sidewalls of the mandrels. The spacers and mandrels defining beta and gamma regions. A beta region includes a beta block mask portion and a gamma region includes a gamma block mask portion of the pattern layer. The method also includes etching a beta pillar over the beta block mask portion and etching a gamma pillar over the gamma block mask portion. The method also includes etching the structure to form a pattern in the pattern layer, the pattern including the gamma and beta block mask portions.

公开(公告)号：US09582629B2

公开(公告)日：2017-02-28

申请号：US14245868

申请日：2014-04-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei Yuan ,  Li Yang ,  Jongwook Kye

IPC: H01L21/76 ,  G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5077

Abstract: At least one method disclosed herein involves creating an overall pattern layout for an integrated circuit that is to be manufactured using a self-aligned double patterning (SADP) process, forming a first metal feature having a first width on a first track of a metal layer using the SADP process, forming a second metal feature having a second width on a second track of the metal layer. The second track is adjacent to the first track. The method also includes forming an electrical connection between the first metal feature and the second metal feature to provide an effectively single metal pattern having a third width that is the sum of the first and second widths, rendering the first and second features decomposable using the SADP process; and decomposing the overall pattern layout with the first and second metal features into a mandrel mask pattern and a block mask pattern.

Abstract translation: 本文公开的至少一种方法涉及为使用自对准双图案（SADP）工艺制造的集成电路的整体图案布局，在金属层的第一轨道上形成具有第一宽度的第一金属特征 使用SADP工艺，在金属层的第二轨道上形成具有第二宽度的第二金属特征。 第二条轨道与第一条轨道相邻。 该方法还包括在第一金属特征和第二金属特征之间形成电连接，以提供具有第三宽度的有效单个金属图案，该第三宽度是第一宽度和第二宽度之和，使得第一和第二特征可以使用SADP分解 处理; 并且将具有第一和第二金属特征的整体图案布局分解成心轴掩模图案和块掩模图案。

公开(公告)号：US09519745B2

公开(公告)日：2016-12-13

申请号：US14523558

申请日：2014-10-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei Yuan ,  Irene Lin ,  Jongwook Kye ,  Mahbub Rashed

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5077 ,  Y02T10/82

Abstract: A method and apparatus for an assisted metal routing is disclosed. Embodiments may include: determining an initial block mask having a first inner vertex for forming a metal routing layer of an integrated circuit (IC); adding an assistant metal portion within the metal routing layer; and determining a modified block mask based on the assistant metal portion for forming the metal routing layer.

Abstract translation: 公开了一种用于辅助金属布线的方法和装置。 实施例可以包括：确定具有用于形成集成电路（IC）的金属布线层的第一内部顶点的初始块掩码; 在所述金属布线层内添加辅助金属部分; 以及基于用于形成金属布线层的辅助金属部分确定修改的块掩模。

公开(公告)号：US09466604B2

公开(公告)日：2016-10-11

申请号：US14540724

申请日：2014-11-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Youngtag Woo ,  Myungjun Lee ,  Ryan Ryoung-Han Kim ,  Jongwook Kye

IPC: H01L29/66 ,  H01L21/82 ,  H01L27/11 ,  H01L27/02 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L27/1104 ,  H01L21/76895 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/5286 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods for utilizing metal segments of an additional metal layer as landing pads for vias and also as local interconnects between contacts in an IC device and resulting devices are disclosed. Embodiments include forming source/drain and gate contacts connected to transistors on a substrate in an integrated circuit device, each contact having an upper surface with a first area; forming metal segments in a plane at the upper surface of the contacts, each metal segment being in contact with one or more of the contacts and having a second area greater than the first area; and forming one or more vias between one or more of the metal segments and one or more first segments of a first metal layer.

Abstract translation: 公开了用于利用附加金属层的金属段作为通孔的着陆焊盘以及IC器件中的触点之间的局部互连以及所产生的器件的方法。 实施例包括在集成电路器件中形成连接到衬底上的晶体管的源极/漏极和栅极触点，每个触点具有带有第一区域的上表面; 在触头的上表面处的平面中形成金属段，每个金属段与一个或多个触点接触并具有大于第一区的第二区; 以及在一个或多个金属段和第一金属层的一个或多个第一段之间形成一个或多个通孔。

公开(公告)号：US09400863B2

公开(公告)日：2016-07-26

申请号：US14687477

申请日：2015-04-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei Yuan ,  Soo Han Choi ,  Li Yang ,  Jongwook Kye

IPC: G06F17/50

CPC classification number: G06F17/5077

Abstract: Methodologies and an apparatus enabling a generation of color undeterminable polygons in IC designs are disclosed. Embodiments include: determining a plurality of first routes extending horizontally in an IC design, each of the plurality of first routes being placed on one of a plurality of equally spaced vertical positions of the IC design; determining whether a second route overlaps one of the vertical positions of the plurality of equally spaced vertical positions; and selecting a design rule for the second route based on the determination of whether the second route overlaps.

公开(公告)号：US09292647B2

公开(公告)日：2016-03-22

申请号：US14163511

申请日：2014-01-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei Yuan ,  Mahbub Rashed ,  Jongwook Kye

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  Y02T10/82

Abstract: A methodology for a modified cell architecture and the resulting devices are disclosed. Embodiments may include determining a first vertical track spacing for a plurality of first routes for an integrated circuit (IC) design, each of the plurality of first routes having a first width, determining a second vertical track spacing for a second route for the IC design, the second route having a second width, and designating a cell vertical dimension for the IC design based on the first and second vertical track spacings.

Abstract translation: 公开了修改的小区体系结构的方法以及所得到的设备。 实施例可以包括确定用于集成电路（IC）设计的多个第一路由的第一垂直轨道间隔，所述多个第一路线中的​​每一条路径具有第一宽度，确定用于IC设计的第二路线的第二垂直轨道间距 所述第二路径具有第二宽度，并且基于所述第一和第二垂直轨道间隔指定所述IC设计的单元垂直尺寸。