公开(公告)号：US10263013B2

公开(公告)日：2019-04-16

申请号：US15441711

申请日：2017-02-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anthony K. Stamper ,  Steven M. Shank ,  Siva P. Adusumilli

IPC: H01L27/12 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/84 ,  H01L49/02 ,  H01L21/265 ,  H01L29/08 ,  H01L29/45 ,  H01L27/06 ,  H01L29/06

Abstract: Disclosed is an integrated circuit (IC) formation method, wherein trenches are formed within a semiconductor layer to define semiconductor mesa(s). Instead of immediately filling the trenches with an isolation material and performing a planarizing process to complete the STI regions prior to device formation, the method initially only form sidewall spacers within the trenches on the exposed sidewalls of the semiconductor mesa(s). After the sidewall spacers are formed, device(s) (e.g., field effect transistor(s), silicon resistor(s), etc.) are formed using the semiconductor mesa(s) and, optionally, additional device(s) (e.g., polysilicon resistor(s)) can be formed within the trenches between adjacent semiconductor mesas. Subsequently, middle of the line (MOL) dielectrics (e.g., a conformal etch stop layer and a blanket interlayer dielectric (ILD) layer) are deposited over the device(s), thereby filling any remaining space within the trenches and completing the STI regions. Also disclosed is an IC structure formed using the method.

公开(公告)号：US20190074364A1

公开(公告)日：2019-03-07

申请号：US15693537

申请日：2017-09-01

Applicant: GLOBALFOUNDRIES INC.

Inventor： Laura J. Schutz ,  Anthony K. Stamper ,  Siva P. Adusumilli ,  Joshua F. Dillon

IPC: H01L29/49 ,  H01L29/417 ,  H01L29/423 ,  H01L21/8234 ,  H01L21/3205 ,  H01L29/66

CPC classification number: H01L29/4991 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/32053 ,  H01L21/76224 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/41758 ,  H01L29/4232 ,  H01L29/4238 ,  H01L29/4933 ,  H01L29/4975 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66568 ,  H01L29/66575

Abstract: A method may include forming a transistor on a substrate, the transistor including a gate, and forming a sacrificial spacer extending along an entirety of a thickness of the gate. A via layer is then formed over/about the gate. The sacrificial spacer is at least partially removed, leaving an air vent opening. An airgap spacer is formed in the dielectric layer by depositing another dielectric layer to close off the air vent opening. The airgap spacer is coincident with at least one sidewall of the gate and extends along an entirety of a thickness of the gate. Gate airgaps may also be provided over the gate. Other embodiments extend the gate and airgap spacer the full thickness of the dielectric layer thereabout. Other embodiments extend the airgap spacer over the gate.

公开(公告)号：US10192779B1

公开(公告)日：2019-01-29

申请号：US15935606

申请日：2018-03-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven M. Shank ,  Anthony K. Stamper ,  Ian McCallum-Cook ,  Siva P. Adusumilli

IPC: H01L21/763 ,  H01L29/06 ,  H01L27/12 ,  H01L27/06 ,  H01L21/762 ,  H01L21/324 ,  H01L21/84 ,  H01L21/265 ,  H01L21/02

Abstract: Structures with altered crystallinity beneath semiconductor devices and methods associated with forming such structures. Trench isolation regions surround an active device region composed of a single-crystal semiconductor material. A non-single-crystal layer has a first section arranged beneath the trench isolation regions and a second section arranged beneath the active device region. The first section of the non-single-crystal layer has a first width in a vertical direction. The second section of the non-single-crystal layer has a second width in the vertical direction that is less than the first width of the first section of the non-single-crystal layer.

公开(公告)号：US10770374B2

公开(公告)日：2020-09-08

申请号：US16255505

申请日：2019-01-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Siva P. Adusumilli ,  Steven M. Shank

IPC: H01L23/48 ,  H01L23/528 ,  H01L21/768 ,  G02B6/12 ,  G02B6/136 ,  G02B6/30 ,  G02B6/132

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to through-silicon vias (TSV) for heterogeneous integration of semiconductor device structures and methods of manufacture. The structure includes: a plurality of cavity structures provided in a single substrate; at least one optical device provided on two sides of the single substrate and between the plurality of cavity structures; and a through wafer optical via extending through the substrate, between the plurality of cavity structures and which exposes a backside of the at least one optical device.

公开(公告)号：US10580893B2

公开(公告)日：2020-03-03

申请号：US15947364

申请日：2018-04-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Siva P. Adusumilli ,  Steven M. Shank ,  Anthony K. Stamper ,  John J. Ellis-Monaghan

IPC: H01L29/78 ,  H01L21/762 ,  H01L21/84 ,  H01L21/324 ,  H01L23/10 ,  H01L29/06 ,  H01L29/10 ,  H01L27/12 ,  H01L21/02 ,  H01L21/8238

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to sealed cavity structures having a non-planar surface features and methods of manufacture. The structure includes a cavity formed in a substrate material. The cavity is covered with epitaxial material that has a non-planar surface topography which imparts a stress component on a transistor.

公开(公告)号：US10461152B2

公开(公告)日：2019-10-29

申请号：US15645655

申请日：2017-07-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anthony K. Stamper ,  Steven M. Shank ,  John J. Ellis-Monaghan ,  Siva P. Adusumilli

IPC: H01L21/764 ,  H01L29/06 ,  H01L23/66 ,  H01L29/10 ,  H01L29/78

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to radio frequency (RF) switches with airgap structures and methods of manufacture. The structure includes a substrate with at least one airgap structure formed in a well region under at least one gate structure, and which extends to a junction formed by a source/drain region of the at least one gate structure.

公开(公告)号：US10163679B1

公开(公告)日：2018-12-25

申请号：US15609742

申请日：2017-05-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Siva P. Adusumilli ,  Steven M. Shank ,  Richard A. Phelps ,  Anthony K. Stamper

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/02

Abstract: Structures for shallow trench isolation regions and methods for forming shallow trench isolation regions. A trench is etched partially through a device layer of a silicon-on-insulator substrate. A section of the device layer at a bottom of the trench is thermally oxidized to form a shallow trench isolation region in the trench. During the thermal oxidation, another region of the device layer may be concurrently oxidized over a partial thickness and, after removal of the oxide from this device layer region, used as a thinned silicon body. Prior to the thermal oxidation process, this device layer region may be implanted with an oxidation-retarding species that decreases its oxidation rate in comparison with the oxidation rate of the section of the device layer used to form the shallow trench isolation region.

公开(公告)号：US11527432B2

公开(公告)日：2022-12-13

申请号：US17086925

申请日：2020-11-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven M. Shank ,  Anthony K. Stamper ,  Ian McCallum-Cook ,  Siva P. Adusumilli

IPC: H01L21/763 ,  H01L29/06 ,  H01L27/12 ,  H01L21/762 ,  H01L21/324 ,  H01L21/84 ,  H01L21/265 ,  H01L21/74 ,  H01L29/32 ,  H01L21/02 ,  H01L27/06 ,  H01L29/10

Abstract: Structures with altered crystallinity beneath semiconductor devices and methods associated with forming such structures. Trench isolation regions surround an active device region composed of a single-crystal semiconductor material. A first non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. A second non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. The first non-single-crystal layer is arranged between the second non-single-crystal layer and the active device region.

公开(公告)号：US10923577B2

公开(公告)日：2021-02-16

申请号：US16241441

申请日：2019-01-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Johnatan A. Kantarovsky ,  Siva P. Adusumilli ,  Vibhor Jain

IPC: H01L29/00 ,  H01L29/51 ,  H01L21/762 ,  H01L49/02 ,  H01L29/161 ,  H01L21/3065 ,  H01L21/02 ,  H01L29/06 ,  H01L21/3105 ,  H01L21/764

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to cavity structures under shallow trench isolation regions and methods of manufacture. The structure includes: one or more cavity structures provided in a substrate material and sealed with an epitaxial material; and a shallow trench isolation region directly above the one or more cavity structures in the substrate material.

公开(公告)号：US20210043624A1

公开(公告)日：2021-02-11

申请号：US16534361

申请日：2019-08-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Siva P. Adusumilli ,  Julien Frougier ,  Ruilong Xie ,  Anthony K. Stamper

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/265 ,  H01L21/324 ,  H01L29/04

Abstract: Structures with altered crystallinity and methods associated with forming such structures. A semiconductor layer has a first region containing polycrystalline semiconductor material, defects, and atoms of an inert gas species. Multiple fins are arranged over the first region of the semiconductor layer. The structure may be formed by implanting the semiconductor layer with inert gas ions to modify a crystal structure of the semiconductor layer in the first region and a second region between the first region and a top surface of the semiconductor layer. An annealing process is used to convert the first region of the semiconductor layer to a polycrystalline state and the second region of the semiconductor layer to a monocrystalline state. The fins are patterned from the second region of the semiconductor layer and another semiconductor layer epitaxially grown over the second region of the semiconductor layer.