公开(公告)号：US20240085247A1

公开(公告)日：2024-03-14

申请号：US17931670

申请日：2022-09-13

Applicant: GlobalFoundries U.S. Inc.

Inventor： Santosh Sharma ,  Michael J. Zierak ,  Steven J. Bentley ,  Johnatan Avraham Kantarovsky

IPC: G01K7/18 ,  H01C7/04 ,  H01L27/06 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L29/778

CPC classification number: G01K7/183 ,  H01C7/041 ,  H01L27/0605 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/402 ,  H01L29/7786

Abstract: A structure includes a negative temperature coefficient (NTC) resistor for use in gallium nitride (GaN) technology. The NTC resistor includes a p-type doped GaN (pGaN) layer, and a gallium nitride (GaN) heterojunction structure under the pGaN layer. The GaN heterojunction structure includes a barrier layer and a channel layer. An isolation region extends across an interface of the barrier layer and the channel layer, and a first metal electrode is on the pGaN layer spaced from a second metal electrode on the pGaN layer. The NTC resistor can be used as a temperature compensated reference in a structure providing a temperature detection circuit. The temperature detection circuit includes an enhancement mode HEMT sharing parts with the NTC resistor and includes temperature independent current sources including depletion mode HEMTs.

公开(公告)号：US20230223425A1

公开(公告)日：2023-07-13

申请号：US18188521

申请日：2023-03-23

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Michael J. Zierak ,  Siva P. Adusumilli ,  Yves T. Ngu ,  Steven M. Shank

IPC: H01L21/20

CPC classification number: H01L28/20

Abstract: Embodiments of the disclosure provide a method, including forming a shallow trench isolation (STI) in a substrate. The method further includes doping the substrate with a noble dopant, thereby forming a disordered crystallographic layer under the STI. The method also includes converting the disordered crystallographic layer to a doped buried polysilicon layer under the STI and a high resistivity (HR) polysilicon layer under the doped buried polysilicon layer. The method includes forming a pair of contacts operatively coupled in a spaced manner to the doped buried polysilicon layer.

公开(公告)号：US20230178449A1

公开(公告)日：2023-06-08

申请号：US17643023

申请日：2021-12-07

Applicant: GlobalFoundries U.S. Inc.

Inventor： Mark D. Levy ,  Rajendran Krishnasamy ,  Michael J. Zierak ,  Siva P. Adusumilli

IPC: H01L23/367 ,  H01L29/732 ,  H01L23/373 ,  H01L29/417

CPC classification number: H01L23/367 ,  H01L29/7325 ,  H01L23/3736 ,  H01L29/41708

Abstract: A structure includes an electrical device, and an active contact landed on a portion of the electrical device. The active contact includes a first body of a first material. A thermal dissipation pillar is adjacent the active contact and unlanded on but over the portion of the electrical device. The thermal dissipation pillar includes a second body of a second material having a higher thermal conductivity than the first material. The thermal dissipation pillar may be in thermal communication with a wire in a dielectric layer over the active contact and the thermal dissipation pillar. The electrical device can be any integrated circuit device that generates heat.

公开(公告)号：US20240105595A1

公开(公告)日：2024-03-28

申请号：US17934389

申请日：2022-09-22

Applicant: GlobalFoundries U.S. Inc.

Inventor： Johnatan A. Kantarovsky ,  Santosh Sharma ,  Michael J. Zierak ,  Steven J. Bentley ,  Ephrem G. Gebreselasie

IPC: H01L23/525 ,  H01L21/76 ,  H01L27/06 ,  H01L29/20

CPC classification number: H01L23/5256 ,  H01L21/7605 ,  H01L27/0605 ,  H01L29/2003

Abstract: Embodiments of the disclosure provide an electrically programmable fuse (efuse) over crystalline semiconductor material. A structure according to the disclosure includes a plurality of crystalline semiconductor layers. Each crystalline semiconductor layer includes a compound material. A metallic layer is on the plurality of crystalline semiconductor layers. The metallic layer has a lower resistivity than an uppermost layer of the plurality of crystalline semiconductor layers. A pair of gate conductors is on respective portions of the metallic layer. The metallic layer defines an electrically programmable fuse (efuse) link between the gate conductors.

公开(公告)号：US20240006309A1

公开(公告)日：2024-01-04

申请号：US17809610

申请日：2022-06-29

Applicant: GlobalFoundries U.S. Inc.

Inventor： Michael J. Hauser ,  Michael J. Zierak

IPC: H01L23/525 ,  H01L23/62 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L23/5256 ,  H01L23/62 ,  H01L23/5226 ,  H01L23/528

Abstract: An integrated circuit (IC) structure includes a transistor in a device layer over a substrate, the transistor including a gate; and a plurality of interconnect layers over the device layer, the plurality of interconnect layers including a last metal layer. A process-induced damage (PID) protection structure includes a conductor coupling the gate to a well in the substrate but includes an open fuse element therein. A first metal interconnect extends from a first terminal of the open fuse element to a first pad in the last metal layer, and a second metal interconnect extending from a second terminal of the open fuse element to a second pad in the last metal layer. The fuse element is closed during fabrication, and the metal interconnects allow opening of the fuse element to deactivate the PID protection structure after fabrication.

公开(公告)号：US11764060B2

公开(公告)日：2023-09-19

申请号：US15584121

申请日：2017-05-02

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Michel J. Abou-Khalil ,  Steven M. Shank ,  Alvin J. Joseph ,  Michael J. Zierak

IPC: H01L21/02 ,  H01L21/762 ,  H01L29/06 ,  H01L29/16 ,  H01L29/04 ,  H01L29/10 ,  H01L21/265 ,  H01L29/78

CPC classification number: H01L21/02667 ,  H01L21/26506 ,  H01L21/76224 ,  H01L29/04 ,  H01L29/0649 ,  H01L29/0688 ,  H01L29/1079 ,  H01L29/1095 ,  H01L29/16 ,  H01L29/78 ,  H01L21/02532 ,  H01L21/02595

Abstract: Device structures for a field-effect transistor and methods of forming a device structure for a field-effect transistor. A trench isolation region is formed in a substrate, and surrounds a semiconductor body. An undercut cavity region is also formed in the substrate. The undercut cavity region extends laterally beneath the semiconductor body and defines a body pedestal as a section of the substrate that is arranged in vertical alignment with the semiconductor body.

公开(公告)号：US11664412B2

公开(公告)日：2023-05-30

申请号：US17155445

申请日：2021-01-22

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Michael J. Zierak ,  Siva P. Adusumilli ,  Yves T. Ngu ,  Steven M. Shank

IPC: H01L21/762 ,  H01L27/06 ,  H01L49/02

CPC classification number: H01L28/20 ,  H01L21/76224 ,  H01L27/0629

Abstract: A structure provides a polysilicon resistor under a shallow trench isolation (STI). The structure includes the STI, a resistor in the form of a doped buried polysilicon layer under the STI, and a high resistivity (HR) polysilicon layer under the doped buried polysilicon layer. The structure also includes a pair of contacts operatively coupled in a spaced manner to the doped buried polysilicon layer. A related method is also disclosed.

公开(公告)号：US11637173B2

公开(公告)日：2023-04-25

申请号：US17036194

申请日：2020-09-29

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Yves T. Ngu ,  Siva P. Adusumilli ,  Steven M. Shank ,  Michael J. Zierak ,  Mickey H. Yu

IPC: H01L49/02 ,  H01L27/12 ,  H01L21/3215 ,  C30B29/06

Abstract: A structure includes a semiconductor substrate, and a polycrystalline resistor region over the semiconductor substrate. The polycrystalline resistor region includes a semiconductor material in a polycrystalline morphology. A dopant-including polycrystalline region is between the polycrystalline resistor region and the semiconductor substrate.

公开(公告)号：US20220238631A1

公开(公告)日：2022-07-28

申请号：US17155445

申请日：2021-01-22

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Michael J. Zierak ,  Siva P. Adusumilli ,  Yves T. Ngu ,  Steven M. Shank

IPC: H01L49/02 ,  H01L21/762

Abstract: A structure provides a polysilicon resistor under a shallow trench isolation (STI). The structure includes the STI, a resistor in the form of a doped buried polysilicon layer under the STI, and a high resistivity (HR) polysilicon layer under the doped buried polysilicon layer. The structure also includes a pair of contacts operatively coupled in a spaced manner to the doped buried polysilicon layer. A related method is also disclosed.