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    Logic circuitry package
    11.
    发明授权
    Logic circuitry package 有权

    公开(公告)号：US11407228B2

    公开(公告)日：2022-08-09

    申请号：US16768321

    申请日：2019-10-25

    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

    Inventor： Scott A. Linn ,  Michael W. Cumbie ,  James Michael Gardner

    IPC: B41J2/175 ,  B41J2/045 ,  G06F13/42 ,  G06F21/44 ,  G06F1/12 ,  G06F1/08 ,  H03K19/0175 ,  B33Y30/00 ,  B29C64/259 ,  G06F3/12 ,  G01F23/24 ,  G01F23/80

    Abstract: A logic circuitry package for a replaceable print apparatus component includes an I2C interface to communicate with a print apparatus logic circuit and at least one logic circuit. The at least one logic circuit is configured to respond to communications over the I2C interface that are directed to an initial or reconfigured I2C address. The at least one logic circuit is configured to receive, via the I2C interface, a write command to a first memory address of the logic circuit to initiate a first function of the logic circuit. The at least one logic circuit is configured to generate first data in response to the first function. The at least one logic circuit is configured to receive, via the I2C interface, a first read command to a second memory address of the logic circuit. The at least one logic circuit is configured to transmit, via the I2C interface, the first data in response to the first read command to the second memory address.

    Logic circuitry
    12.
    发明授权
    Logic circuitry 有权

    公开(公告)号：US11364716B2

    公开(公告)日：2022-06-21

    申请号：US16771092

    申请日：2018-12-03

    Applicant: Hewlett-Packard Development Company, L.P.

    Inventor： Stephen D. Panshin ,  Jefferson P. Ward ,  Scott A. Linn ,  James Michael Gardner

    IPC: B41J2/045 ,  B41J2/175 ,  G06F13/42

    Abstract: In an example, a logic circuitry package is configured to be addressable via a first address and at least one second address and comprises a first logic circuit. The first address may be an address for the first logic circuit, and the package may be configured such that, in response to a first command indicative of a first command time period sent to the first address, the package is accessible via at least one second address for a duration of the first command time period; and in response to a second command indicative of a second command time period sent to the first address, the first logic circuit is to, for a duration of the second command time period, disregard traffic sent to the first address.

    Logic circuitry for a replicable print cartridge
    15.
    发明授权
    Logic circuitry for a replicable print cartridge 有权

    公开(公告)号：US11068434B2

    公开(公告)日：2021-07-20

    申请号：US16781052

    申请日：2020-02-04

    Applicant: Hewlett-Packard Development Company, L.P.

    Inventor： Stephen D. Panshin ,  Scott A. Linn

    IPC: G06F13/42 ,  B41J2/175 ,  G03G21/18 ,  G06F13/38 ,  H04N1/00

    Abstract: Logic circuitry packages for association with replaceable print apparatus components are disclosed herein. An example logic circuitry package includes a timer and a serial data bus interface including a data contact and a clock contact, the serial data bus interface to interface with a serial data bus of a printer. The example logic circuitry package also includes logic circuitry to, in response to a first command sent to the logic circuitry package via the serial data bus of the printer: initiate a low voltage on the data contact; wait for a time period tracked by the timer to expire, without reference to a clock signal at the clock contact from the serial data bus; and upon expiration of the time period, cause the data contact to assume a second voltage different than the low voltage. The first command specifies a duration of the time period and the example logic circuitry is to maintain the low voltage on the data contact based on the duration of the time period.

    Fluidic die
    19.
    发明授权
    Fluidic die 有权

    公开(公告)号：US10232610B2

    公开(公告)日：2019-03-19

    申请号：US15687694

    申请日：2017-08-28

    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

    Inventor： Daryl E. Anderson ,  George H. Corrigan ,  Scott A. Linn

    IPC: B41J2/14 ,  B41J2/045 ,  B41J2/155 ,  B41J2/175

    Abstract: A fluidic die includes a number of sensors to measure properties of a number of property control elements associated with the printhead die, a pass gate to communicate a number of signals to an application specific integrated circuit (ASIC) via an analog bus using control logic associated with the pass gate, and a bi-directional configuration bus coupled to the fluidic die to transmit a number of control signals to property control elements located on the fluidic die.

    Piezoelectric fluid ejection assembly
    20.
    发明授权
    Piezoelectric fluid ejection assembly 有权

    公开(公告)号：US10112390B2

    公开(公告)日：2018-10-30

    申请号：US15822348

    申请日：2017-11-27

    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

    Inventor： Peter J. Fricke ,  Andrew L. Van Brocklin ,  Scott A. Linn

    IPC: B41J2/14 ,  B41J2/045 ,  B41J2/155

    Abstract: In some examples, a piezoelectric fluid ejection assembly includes a micro-electro mechanical system (MEMS) die including a plurality of nozzles, a first application-specific integrated circuit (ASIC) die electrically connected to the MEMS die, and a second ASIC die electrically connected to the MEMS die. The first ASIC die includes a plurality of driver amplifiers for respective nozzles of a first number of the plurality of nozzles, and a plurality of unique waveform data generators to generate respective different waveforms for activating the nozzles of the first number of the plurality of nozzles.

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