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公开(公告)号：US20230063094A1
公开(公告)日：2023-03-02
申请号：US17885157
申请日：2022-08-10
Applicant: Hamilton Sundstrand Corporation
Inventor： Nageswara Rao Kalluri , Sridhar Katakam , Surendra Somasekhar Valleru , Rajkumar Perumal , Pravinsharma Kaliyannan Eswaran
Abstract: A holdup energy arrangement can include a motor control module configured to connect to motor power electronics to operate an inverter to control a motor. The motor control module can operate at a lower voltage than the motor power electronics. The arrangement can include a power supply operatively connected to the motor control module and configured to provide power the motor control module and a converter operatively connected to the power supply and configured to be electrically connected to a DC link capacitor of the motor power electronics. The arrangement can also include a logic control module configured to control the converter to selectively allow energy to flow from the DC link capacitor, through the converter, and to the power supply to provide holdup energy to the power supply with energy from the DC link capacitor.
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公开(公告)号：US12204485B2
公开(公告)日：2025-01-21
申请号：US18363253
申请日：2023-08-01
Applicant: Hamilton Sundstrand Corporation
Inventor： Pravinsharma Kaliyannan Eswaran , Annamalai Nallathambi , Sneha Ashok Moon , Akansha Bhosle
IPC: G06F13/42
Abstract: An asynchronous communication system configured to operate a MIL-1553 protocol. The system includes: a bus; a bus controller coupled to the bus that is configured to control access to the bus; a remote terminal connected to the bus; a device controller connected to the remote terminal; and a read/write overlap avoidance latch connected to the remote terminal. The read/write overlap avoidance latch provides an active signal to the device controller that prevents the device controller from writing data to the remote terminal while the bus controller is reading data from the device controller during a read cycle.
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Patent Agency Ranking
公开(公告)号：US12055390B2
公开(公告)日：2024-08-06
申请号：US17752939
申请日：2022-05-25
Applicant: Hamilton Sundstrand Corporation
Inventor： Pravinsharma Kaliyannan Eswaran , Nageswara Rao Kalluri , Surendra Somasekhar Valleru , Sridhar Katakam , Rajkumar Perumal
IPC: G01B7/30
CPC classification number: G01B7/30
Abstract: A system and method for testing a resolver circuit is provided. Aspects include a resolver circuit including an excitation signal output, a sine signal input, and a cosine signal input, a switching matrix comprising an excitation input connected to the excitation signal output, a first output connected to the sine signal input, and a second output connected to the cosine signal input, wherein the switching matrix further includes a set of switches configured to route an excitation signal from the resolver circuit to mimic a sine and cosine signal output corresponding to a specified angle for a resolver sensor, a controller configured to operate the resolver circuit to output an excitation signal, determine an angle value based on a sine signal received and a cosine signal received from the switching matrix, and compare the angle value to the specified angle to determine a fault condition in the resolver circuit.
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公开(公告)号：US12013420B2
公开(公告)日：2024-06-18
申请号：US17749220
申请日：2022-05-20
Applicant: Hamilton Sundstrand Corporation
Inventor： Nageswara Rao Kalluri , David Frederick Brookes , Sridhar Katakam , Surendra Somasekhar Valleru , Pravinsharma Kaliyannan Eswaran
CPC classification number: G01R19/0038 , H03K5/24
Abstract: A voltage measurement system and method is provided. Aspects include a comparator having a positive and a negative input terminal, a processor configured to supply a reference voltage signal to the negative input terminal, wherein the positive input terminal receives an input voltage, setting the reference voltage signal to a zero voltage signal, determine a line frequency of the input voltage based on a timing signal from the comparator and determining a first pulse width of the input signal based on the timing signal, set the reference voltage to a PWM signal with a fixed duty cycle, receive the timing signal from the output of the comparator, determine a rising edge and a falling edge associated with the input voltage based on the timing signal, and determine a peak value of the input voltage based on a second pulse width between the rising and falling edge.
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15.发明授权公开(公告)号：US11754420B2
公开(公告)日：2023-09-12
申请号：US17169974
申请日：2021-02-08
Applicant: Hamilton Sundstrand Corporation
Inventor： Nageswara Rao Kalluri , Sridhar Katakam , Somasekhar Valleru , Pravinsharma Kaliyannan Eswaran , Rajkumar Perumal
CPC classification number: G01D5/2291 , H01F21/06 , H03G3/3089 , H03G2201/103
Abstract: System and methods for accuracy improvement of an LVDT are provided. Aspects include determining a first voltage from the first PGA and a second voltage from the second PGA, wherein the first voltage is determined from a PGA coupled to a first secondary winding, and wherein the second voltage is determined from a second PGA coupled to a second secondary winding, iteratively performing: analyzing the first voltage to determine a gain correction is needed for a first gain for the first PGA, the gain correction comprising change to the first gain, and analyzing the second voltage to determine a gain correction is needed for a second gain for the second PGA, the gain correction comprising change to the second gain, based on determining a gain correction is not needed for the first gain and the second gain, calculating a position based on the first voltage and the second voltage.
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公开(公告)号：US20230231504A1
公开(公告)日：2023-07-20
申请号：US17994688
申请日：2022-11-28
Applicant: Hamilton Sundstrand Corporation
Inventor： Pravinsharma Kaliyannan Eswaran , Nageswara Rao Kalluri , David Frederick Brookes , Sridhar Katakam , Surendra Somasekhar Valleru
IPC: H02P27/08
CPC classification number: H02P27/08 , H02P2201/03
Abstract: A motor drive system includes a direct current (DC) bus that provides a DC link voltage across a DC link capacitor, and a split DC link mid-point circuit connected in parallel with the DC link capacitor. The split DC link mid-point circuit establishes a mid-point reference based on the DC link voltage. A power inverter is in signal communication with the DC bus. The power inverter includes one or more gate driver units configured to drive one or more corresponding switches. Each gate driver unit includes a mid-point ground connection that is connected to the mid-point reference. The split DC link mid-point circuit can define a voltage divide that establishes the mid-point reference and can be used to monitor the DC link voltage.
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17.发明申请公开(公告)号：US20220187103A1
公开(公告)日：2022-06-16
申请号：US17169974
申请日：2021-02-08
Applicant: Hamilton Sundstrand Corporation
Inventor： Nageswara Rao Kalluri , Sridhar Katakam , Somasekhar Valleru , Pravinsharma Kaliyannan Eswaran , Rajkumar Perumal
Abstract: System and methods for accuracy improvement of an LVDT are provided. Aspects include determining a first voltage from the first PGA and a second voltage from the second PGA, wherein the first voltage is determined from a PGA coupled to a first secondary winding, and wherein the second voltage is determined from a second PGA coupled to a second secondary winding, iteratively performing: analyzing the first voltage to determine a gain correction is needed for a first gain for the first PGA, the gain correction comprising change to the first gain, and analyzing the second voltage to determine a gain correction is needed for a second gain for the second PGA, the gain correction comprising change to the second gain, based on determining a gain correction is not needed for the first gain and the second gain, calculating a position based on the first voltage and the second voltage.
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