公开(公告)号：US10733690B2

公开(公告)日：2020-08-04

申请号：US15982693

申请日：2018-05-17

Applicant: Intel Corporation

Inventor： John Gierach ,  Abhishek Venkatesh ,  Travis Schluessler ,  Devan Burke ,  Tomer Bar-On ,  Michael Apodaca

IPC: G06T1/20 ,  G06T17/10

Abstract: Embodiments are generally directed to GPU mixed primitive topology type processing. An embodiment of an apparatus includes one or more processor cores; and a memory to store data for graphics processing, wherein the one or more processing cores are to generate in the memory a vertex buffer to store vertex data for a mesh to be rendered and an index buffer to index the vertex data stored in the vertex buffer, the index buffer being structured to include index data for multiple primitive topology types. The one or more processor cores are to process the index data for the plurality of primitive topology types from the index buffer and fetch vertex data from the vertex buffer; and are to set up each primitive topology type of the plurality of primitive topology types for processing in a single draw operation.

公开(公告)号：US20200210238A1

公开(公告)日：2020-07-02

申请号：US16726341

申请日：2019-12-24

Applicant: Intel Corporation

Inventor： Abhishek R Appu ,  Altug Koker ,  Balaji Vembu ,  Joydeep Ray ,  Kamal Sinha ,  Prasoonkumar Surti ,  Kiran C. Veernapu ,  Subramaniam Maiyuran ,  Sanjeev S. Jahagirdar ,  Eric J. Asperheim ,  Guei-Yuan Lueh ,  David Puffer ,  Wenyin Fu ,  Nikos Kaburlasos ,  Bhushan M. Borole ,  Josh B. Mastronarde ,  Linda L. Hurd ,  Travis T. Schluessler ,  Tomasz Janczak ,  Abhishek Venkatesh ,  Kai Xiao ,  Slawomir Grajewski

IPC: G06F9/50 ,  G06T15/00 ,  G06T1/60 ,  G06T1/20 ,  G06F9/48 ,  G06F1/329

Abstract: In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to analyze a workload and assign the workload to one of the first type of execution unit or the second type of execution unit. Other embodiments are also disclosed and claimed.

公开(公告)号：US10573066B2

公开(公告)日：2020-02-25

申请号：US16215850

申请日：2018-12-11

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Karthik Vaidyanathan ,  Murali Ramadoss ,  Michael Apodaca ,  Abhishek Venkatesh ,  Joydeep Ray ,  Abhishek R. Appu

IPC: G06T15/50 ,  G06T15/00 ,  G06T15/80 ,  G06T17/20

Abstract: Systems, apparatuses and methods may provide away to render edges of an object defined by multiple tessellation triangles. More particularly, systems, apparatuses and methods may provide a way to perform anti-aliasing at the edges of the object based on a coarse pixel rate, where the coarse pixels may be based on a coarse Z value indicate a resolution or granularity of detail of the coarse pixel. The systems, apparatuses and methods may use a shader dispatch engine to dispatch raster rules to a pixel shader to direct the pixel shader to include, in a tile and/or tessellation triangle, one more finer coarse pixels based on a percent of coverage provided by a finer coarse pixel of a tessellation triangle at or along the edge of the object.

公开(公告)号：US20190355084A1

公开(公告)日：2019-11-21

申请号：US15982693

申请日：2018-05-17

Applicant: Intel Corporation

Inventor： John Gierach ,  Abhishek Venkatesh ,  Travis Schluessler ,  Devan Burke ,  Tomer Bar-On ,  Michael Apodaca

IPC: G06T1/20 ,  G06T17/10

Abstract: Embodiments are generally directed to GPU mixed primitive topology type processing. An embodiment of an apparatus includes one or more processor cores; and a memory to store data for graphics processing, wherein the one or more processing cores are to generate in the memory a vertex buffer to store vertex data for a mesh to be rendered and an index buffer to index the vertex data stored in the vertex buffer, the index buffer being structured to include index data for multiple primitive topology types. The one or more processor cores are to process the index data for the plurality of primitive topology types from the index buffer and fetch vertex data from the vertex buffer; and are to set up each primitive topology type of the plurality of primitive topology types for processing in a single draw operation.

公开(公告)号：US10445923B2

公开(公告)日：2019-10-15

申请号：US15719381

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Devan Burke ,  Abhishek Venkatesh ,  Travis Schluessler

IPC: G06T15/04 ,  G06T15/00 ,  G06T15/80

Abstract: One embodiment provides a graphics processor comprising a hardware graphics rendering pipeline configured to perform multisample anti-aliasing, the hardware graphics rendering pipeline including pixel processing logic to determine that each sample location of a pixel of a multisample surface is associated with a clear value and resolve a color value for the pixel to a non-multisample surface via a write of metadata to indicate that the pixel has the clear value.

公开(公告)号：US20190096117A1

公开(公告)日：2019-03-28

申请号：US15719381

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Devan Burke ,  Abhishek Venkatesh ,  Travis Schluessler

IPC: G06T15/04 ,  G06T15/80 ,  G06T15/00

CPC classification number: G06T15/04 ,  G06T15/005 ,  G06T15/80

Abstract: One embodiment provides a graphics processor comprising a hardware graphics rendering pipeline configured to perform multisample anti-aliasing, the hardware graphics rendering pipeline including pixel processing logic to determine that each sample location of a pixel of a multisample surface is associated with a clear value and resolve a color value for the pixel to a non-multisample surface via a write of metadata to indicate that the pixel has the clear value.

公开(公告)号：US11762696B2

公开(公告)日：2023-09-19

申请号：US17520583

申请日：2021-11-05

Applicant: Intel Corporation

Inventor： Abhishek R Appu ,  Altug Koker ,  Balaji Vembu ,  Joydeep Ray ,  Kamal Sinha ,  Prasoonkumar Surti ,  Kiran C. Veernapu ,  Subramaniam Maiyuran ,  Sanjeev S. Jahagirdar ,  Eric J. Asperheim ,  Guei-Yuan Lueh ,  David Puffer ,  Wenyin Fu ,  Nikos Kaburlasos ,  Bhushan M. Borole ,  Josh B. Mastronarde ,  Linda L. Hurd ,  Travis T. Schluessler ,  Tomasz Janczak ,  Abhishek Venkatesh ,  Kai Xiao ,  Slawomir Grajewski

IPC: G06F9/50 ,  G06F1/329 ,  G06F9/48 ,  G06T1/20 ,  G06T1/60 ,  G06T15/00

CPC classification number: G06F9/5016 ,  G06F1/329 ,  G06F9/4893 ,  G06F9/5044 ,  G06T1/20 ,  G06T1/60 ,  G06T15/005 ,  G06T2200/28 ,  Y02D10/00

Abstract: In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to analyze a workload and assign the workload to one of the first type of execution unit or the second type of execution unit. Other embodiments are also disclosed and claimed.

公开(公告)号：US11663774B2

公开(公告)日：2023-05-30

申请号：US17684686

申请日：2022-03-02

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Karthik Vaidyanathan ,  Murali Ramadoss ,  Michael Apodaca ,  Abhishek Venkatesh ,  Joydeep Ray ,  Abhishek R. Appu

IPC: G06T15/50 ,  G06T15/00 ,  G06T15/80 ,  G06T17/20

CPC classification number: G06T15/503 ,  G06T15/005 ,  G06T15/80 ,  G06T17/205 ,  G06T2200/12

Abstract: Systems, apparatuses and methods may provide away to render edges of an object defined by multiple tessellation triangles. More particularly, systems, apparatuses and methods may provide a way to perform anti-aliasing at the edges of the object based on a coarse pixel rate, where the coarse pixels may be based on a coarse Z value indicate a resolution or granularity of detail of the coarse pixel. The systems, apparatuses and methods may use a shader dispatch engine to dispatch raster rules to a pixel shader to direct the pixel shader to include, in a tile and/or tessellation triangle, one more finer coarse pixels based on a percent of coverage provided by a finer coarse pixel of a tessellation triangle at or along the edge of the object.

公开(公告)号：US20230140640A1

公开(公告)日：2023-05-04

申请号：US17518328

申请日：2021-11-03

Applicant: Intel Corporation

Inventor： Stav Gurtovoy ,  Abhishek Venkatesh ,  Michael Apodaca ,  Travis Schluessler ,  John Feit

IPC: G06T15/00 ,  G06T1/20 ,  G06T1/60 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538

Abstract: Methods, systems and apparatuses may provide for technology that marks a graphics resource as a flush candidate during a current frame, conducts an early flush of a command buffer from the graphics resource if a write event is detected with respect to the graphics resource during a subsequent frame, and bypasses the early flush if the write event is not detected with respect to the graphics resource during the subsequent frame. In one example, the graphics resource is marked as the flush candidate in response to a read back operation of the host processor with respect to the graphics resource, wherein the read back operation retrieves a query result and/or maps a staging resource.

公开(公告)号：US20220172316A1

公开(公告)日：2022-06-02

申请号：US17486330

申请日：2021-09-27

Applicant: Intel Corporation

Inventor： Abhishek Venkatesh ,  Karthik Vaidyanathan ,  Murali Ramadoss ,  Michael Apodaca ,  Prasoonkumar Surti

IPC: G06T1/20 ,  G06F9/30 ,  G06F9/38 ,  G06T15/00

Abstract: An embodiment of a graphics command coordinator apparatus may include a commonality identifier to identify a commonality between a first graphics command corresponding to a first frame and a second graphics command corresponding to a second frame, a commonality analyzer communicatively coupled to the commonality identifier to determine if the first graphics command and the second graphics command can be processed together based on the commonality identified by the commonality identifier, and a commonality indicator communicatively coupled to the commonality analyzer to provide an indication that the first graphics command and the second graphics command are to be processed together. Other embodiments are disclosed and claimed.