公开(公告)号：US20200006293A1

公开(公告)日：2020-01-02

申请号：US16024700

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Robert SANKMAN ,  Sanka GANESAN ,  Bernd WAIDHAS ,  Thomas WAGNER ,  Lizabeth KESER

IPC: H01L25/065

Abstract: Embodiments disclosed herein include an electronics package comprising stacked dies. In an embodiment, the electronics package comprises a first die that includes a plurality of first conductive interconnects extending out from a first surface of the first die. In an embodiment, the first die further comprises a keep out zone. In an embodiment, the electronic package may also comprise a second die. In an embodiment, the second die is positioned entirely within a perimeter of the keep out zone of the first die. In an embodiment, a first surface of the second die faces the first surface of the first die.

公开(公告)号：US20240363567A1

公开(公告)日：2024-10-31

申请号：US18140465

申请日：2023-04-27

Applicant: Intel Corporation

Inventor： Bernd WAIDHAS ,  Thomas WAGNER ,  Georg SEIDEMANN ,  Harald GOSSNER ,  Telesphor KAMGAING ,  Shuhei YAMADA ,  Tae Young YANG

IPC: H01L23/00 ,  H01Q1/22 ,  H01Q1/38

CPC classification number: H01L24/08 ,  H01L24/05 ,  H01Q1/2283 ,  H01Q1/38 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L2224/05647 ,  H01L2224/08265 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/2919 ,  H01L2224/32013 ,  H01L2224/32265 ,  H01L2924/0665

Abstract: Embodiments disclosed herein include a die module. In an embodiment, the die module comprises a die with a first surface and a second surface. In an embodiment, a first pad is on the second surface of the die, where a top surface of the first pad is substantially coplanar with the second surface. In an embodiment, the die module comprises an antenna module with a third surface and a fourth surface. In an embodiment, a second pad is on the third surface of the antenna module, where a bottom surface of the second pad is substantially coplanar with the third surface. In an embodiment, the top surface of the first pad directly contacts the bottom surface of the second pad.

公开(公告)号：US20240194552A1

公开(公告)日：2024-06-13

申请号：US18587331

申请日：2024-02-26

Applicant: Intel Corporation

Inventor： Lizabeth KESER ,  Bernd WAIDHAS ,  Thomas ORT ,  Thomas WAGNER

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/522

CPC classification number: H01L23/3114 ,  H01L21/568 ,  H01L23/5226 ,  H01L24/11 ,  H01L24/14 ,  H01L24/96 ,  H01L28/10 ,  H01L28/40 ,  H01L2224/02379 ,  H01L2924/19011

Abstract: A semiconductor device and method of including peripheral devices into a package is disclosed. In one example, a peripheral device includes a passive device such as a capacitor or an inductor. Examples are shown that include a peripheral device that is substantially the same thickness as a die or a die assembly. Examples are further shown that use this configuration in a fan out process to form semiconductor devices.

公开(公告)号：US20240128202A1

公开(公告)日：2024-04-18

申请号：US18397898

申请日：2023-12-27

Applicant: Intel Corporation

Inventor： Gianni SIGNORINI ,  Georg SEIDEMANN ,  Bernd WAIDHAS

IPC: H01L23/552 ,  H01L21/48 ,  H01L21/78 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L23/552 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838

Abstract: Embodiments disclosed herein include electronic packages with conformal shields and methods of forming such packages. In an embodiment, the electronic package comprises a die having a first surface, a second surface opposite the first surface, and sidewall surfaces. A redistribution layer is over the first surface of the die, and the redistribution layer comprises a first conductive layer. In an embodiment, an under ball metallization (UBM) layer is over the redistribution layer, and a conductive shield is over the sidewall surfaces of the die and the second surface of the die. In an embodiment, the conductive shield is electrically coupled to the UBM layer.

公开(公告)号：US20230197566A1

公开(公告)日：2023-06-22

申请号：US17644802

申请日：2021-12-17

Applicant: Intel Corporation

Inventor： Bernd WAIDHAS ,  Wolfgang MOLZER ,  Peter BAUMGARTNER ,  Thomas WAGNER ,  Joachim SINGER ,  Klaus HEROLD ,  Michael LANGENBUCH

IPC: H01L23/433 ,  H01L23/473 ,  H01L23/40 ,  H01L21/48

CPC classification number: H01L23/433 ,  H01L21/4871 ,  H01L23/473 ,  H01L23/4012 ,  H01L2023/4068

Abstract: A semiconductor die is provided. The semiconductor die includes a plurality of transistors arranged at a front side of a semiconductor substrate and an electrically conductive structure and a trench extending from a backside of the semiconductor substrate into the semiconductor substrate. A length of the trench is equal or larger than a lateral dimension of the semiconductor substrate.

公开(公告)号：US20230094594A1

公开(公告)日：2023-03-30

申请号：US17448732

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Wolfgang MOLZER ,  Klaus HEROLD ,  Joachim SINGER ,  Peter BAUMGARTNER ,  Michael LANGENBUCH ,  Thomas WAGNER ,  Bernd WAIDHAS

IPC: H01L25/065 ,  H01L27/088 ,  H01L23/498 ,  H01L23/367

Abstract: A semiconductor device is disclosed, comprising a first semiconductor die comprising a plurality of transistors; a second semiconductor die comprising power supply circuitry configured to generate a supply voltage for the plurality of transistors of the first semiconductor die; and a heat spreader structure. A power supply routing for a reference voltage or a power supply voltage which extends from the heat spreader structure through the second semiconductor die to the first semiconductor die.

公开(公告)号：US20200098698A1

公开(公告)日：2020-03-26

申请号：US16143212

申请日：2018-09-26

Applicant: Intel Corporation

Inventor： Richard PATTEN ,  David O'SULLIVAN ,  Georg SEIDEMANN ,  Bernd WAIDHAS

IPC: H01L23/552 ,  H01L23/31 ,  H01L23/522

Abstract: Embodiments include semiconductor packages, such as wafer level chip scale packages (WLCSPs), flip chip chip scale packages (FCCSPs), and fan out packages. The WLCSP includes a first doped region on a second doped region, a dielectric on a redistribution layer, where the dielectric is between the redistribution layer and doped regions. The WLCSP also includes a shield over the doped regions, the dielectric, and the redistribution layer, where the shield includes a plurality of surfaces, and at least one of the plurality of surfaces of the shield is on a top surface of the first doped region. The WLCSP may have interconnects coupled to the second doped region and redistribution layer. The shield may be a conductive shield that is coupled to ground, and the shield may be directly coupled to the redistribution layer and first doped region. The first and second doped regions may include highly doped n-type materials.

公开(公告)号：US20250167183A1

公开(公告)日：2025-05-22

申请号：US19034153

申请日：2025-01-22

Applicant: Intel Corporation

Inventor： David O'SULLIVAN ,  Georg SEIDEMANN ,  Richard PATTEN ,  Bernd WAIDHAS

IPC: H01L25/10 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L25/00

Abstract: Embodiments include semiconductor packages and a method of forming the semiconductor packages. A semiconductor package includes a mold over and around a first die and a first via. The semiconductor package has a conductive pad of a first redistribution layer disposed on a top surface of the first die and/or a top surface of the mold. The semiconductor package includes a second die having a solder ball coupled to a die pad on a bottom surface of the second die, where the solder ball of the second die is coupled to the first redistribution layer. The first redistribution layer couples the second die to the first die, where the second die has a first edge and a second edge, and where the first edge is positioned within a footprint of the first die and the second edge is positioned outside the footprint of the first die.

公开(公告)号：US20240364000A1

公开(公告)日：2024-10-31

申请号：US18140361

申请日：2023-04-27

Applicant: Intel Corporation

Inventor： Bernd WAIDHAS ,  Thomas WAGNER ,  Georg SEIDEMANN ,  Harald GOSSNER ,  Telesphor KAMGAING ,  Shuhei YAMADA ,  Tae Young YANG

IPC: H01Q1/42 ,  H01Q1/22 ,  H01Q9/04

CPC classification number: H01Q1/422 ,  H01Q1/2283 ,  H01Q9/0407

Abstract: Embodiments disclosed herein include a die module. In an embodiment, the die module comprises a die with a first surface and a second surface. In an embodiment, a first pad is on the second surface of the die, and a dielectric layer is over the second surface of the die and the first pad. In an embodiment, an antenna module is over the dielectric layer, where the antenna module comprises a second pad that is aligned over the first pad.

公开(公告)号：US20230317621A1

公开(公告)日：2023-10-05

申请号：US17707708

申请日：2022-03-29

Applicant: Intel Corporation

Inventor： Bernd WAIDHAS ,  David O'SULLIVAN ,  Georg SEIDEMANN

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/15 ,  H01L25/065 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L23/5384 ,  H01L24/08 ,  H01L23/5383 ,  H01L23/15 ,  H01L25/0655 ,  H01L24/05 ,  H01L24/80 ,  H01L23/49811 ,  H01L21/486 ,  H01L2224/08225 ,  H01L2224/05647 ,  H01L2224/80447 ,  H01L2224/80895

Abstract: Embodiments herein relate to systems, apparatuses, techniques, or processes directed to semiconductor packages that include a glass interposer that includes electrically conductive through glass vias that extend through the interposer. One or more dies may be hybrid bonded to a first side of the glass interposer. In embodiments, the second side of the glass interposer may include a redistribution layer that is electrically coupled with the one or more dies through the through glass vias. Other embodiments may be described and/or claimed.