公开(公告)号：US10929323B2

公开(公告)日：2021-02-23

申请号：US16601137

申请日：2019-10-14

Applicant: Intel Corporation

Inventor： Ren Wang ,  Yipeng Wang ,  Andrew Herdrich ,  Jr-Shian Tsai ,  Tsung-Yuan C. Tai ,  Niall D. McDonnell ,  Hugh Wilkinson ,  Bradley A. Burres ,  Bruce Richardson ,  Namakkal N. Venkatesan ,  Debra Bernstein ,  Edwin Verplanke ,  Stephen R. Van Doren ,  An Yan ,  Andrew Cunningham ,  David Sonnier ,  Gage Eads ,  James T. Clee ,  Jamison D. Whitesell ,  Jerry Pirog ,  Jonathan Kenny ,  Joseph R. Hasting ,  Narender Vangati ,  Stephen Miller ,  Te K. Ma ,  William Burroughs

IPC: G06F13/37 ,  G06F9/54 ,  G06F12/0868 ,  G06F12/0811 ,  G06F13/16 ,  G06F12/04 ,  G06F9/38

Abstract: Apparatus and methods implementing a hardware queue management device for reducing inter-core data transfer overhead by offloading request management and data coherency tasks from the CPU cores. The apparatus include multi-core processors, a shared L3 or last-level cache (“LLC”), and a hardware queue management device to receive, store, and process inter-core data transfer requests. The hardware queue management device further comprises a resource management system to control the rate in which the cores may submit requests to reduce core stalls and dropped requests. Additionally, software instructions are introduced to optimize communication between the cores and the queue management device.

公开(公告)号：US20160019178A1

公开(公告)日：2016-01-21

申请号：US14809423

申请日：2015-07-27

Applicant: Intel Corporation

Inventor： Gilbert Wolrich ,  Debra Bernstein ,  Daniel Cutter ,  Christopher Dolan ,  Matthew J. Adiletta

IPC: G06F13/40 ,  G06F13/28 ,  G06F3/06

CPC classification number: G06F13/20 ,  G06F3/0622 ,  G06F3/0661 ,  G06F3/0679 ,  G06F12/0223 ,  G06F12/0284 ,  G06F12/06 ,  G06F12/0806 ,  G06F12/10 ,  G06F12/109 ,  G06F13/28 ,  G06F13/4027 ,  G06F15/17318 ,  G06F15/76 ,  G06F2212/1041 ,  G06F2212/206 ,  G06F2212/251 ,  G11C7/1033 ,  G11C7/1072

Abstract: The disclosure includes, in general, among other aspects, an apparatus having multiple programmable units integrated within a processor. The apparatus has circuitry to map addresses in a single address space to resources within the multiple programmable units where the single address space includes addresses for different ones of the resources in different ones of the multiple programmable units and where there is a one-to-one correspondence between respective addresses in the single address space and resources within the multiple programmable units.

公开(公告)号：US10761979B2

公开(公告)日：2020-09-01

申请号：US15201303

申请日：2016-07-01

Applicant: Intel Corporation

Inventor： Hugh Wilkinson ,  William R. Wheeler ,  Debra Bernstein

IPC: G06F12/02 ,  G06F9/30 ,  G11C7/10

Abstract: A processor of an aspect includes a register to store a condition code bit, and a decode unit to decode a bit check instruction. The bit check instruction is to indicate a first source operand that is to include a first bit, and is to indicate a check bit value for the first bit. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the bit check instruction, is to compare the first bit with the check bit value, and update a condition code bit to indicate whether the first bit equals or does not equal the check bit value. Other processors, methods, systems, and instructions are disclosed.

公开(公告)号：US20200042479A1

公开(公告)日：2020-02-06

申请号：US16601137

申请日：2019-10-14

Applicant: Intel Corporation

Inventor： Ren Wang ,  Yipeng Wang ,  Andrew Herdrich ,  Jr-Shian Tsai ,  Tsung-Yuan C. Tai ,  Niall D. McDonnell ,  Hugh Wilkinson ,  Bradley A. Burres ,  Bruce Richardson ,  Namakkal N. Venkatesan ,  Debra Bernstein ,  Edwin Verplanke ,  Stephen R. Van Doren ,  An Yan ,  Andrew Cunningham ,  David Sonnier ,  Gage Eads ,  James T. Clee ,  Jamison D. Whitesell ,  Jerry Pirog ,  Jonathan Kenny ,  Joseph R. Hasting ,  Narender Vangati ,  Stephen Miller ,  Te K. Ma ,  William Burroughs

IPC: G06F13/37 ,  G06F12/0811 ,  G06F13/16 ,  G06F9/54 ,  G06F12/0868

Abstract: Apparatus and methods implementing a hardware queue management device for reducing inter-core data transfer overhead by offloading request management and data coherency tasks from the CPU cores. The apparatus include multi-core processors, a shared L3 or last-level cache (“LLC”), and a hardware queue management device to receive, store, and process inter-core data transfer requests. The hardware queue management device further comprises a resource management system to control the rate in which the cores may submit requests to reduce core stalls and dropped requests. Additionally, software instructions are introduced to optimize communication between the cores and the queue management device.

公开(公告)号：US10216668B2

公开(公告)日：2019-02-26

申请号：US15087154

申请日：2016-03-31

Applicant: Intel Corporation

Inventor： Ren Wang ,  Yipeng Wang ,  Jr-Shian Tsai ,  Andrew Herdrich ,  Tsung-Yuan Tai ,  Niall McDonnell ,  Stephen Van Doren ,  David Sonnier ,  Debra Bernstein ,  Hugh Wilkinson ,  Narender Vangati ,  Stephen Miller ,  Gage Eads ,  Andrew Cunningham ,  Jonathan Kenny ,  Bruce Richardson ,  William Burroughs ,  Joseph Hasting ,  An Yan ,  James Clee ,  Te Ma ,  Jerry Pirog ,  Jamison Whitesell

IPC: G06F13/24 ,  G06F13/36 ,  G06F13/40 ,  G06F12/1027

Abstract: Technologies for a distributed hardware queue manager include a compute device having a processor. The processor includes two or more hardware queue managers as well as two or more processor cores. Each processor core can enqueue or dequeue data from the hardware queue manager. Each hardware queue manager can be configured to contain several queue data structures. In some embodiments, the queues are addressed by the processor cores using virtual queue addresses, which are translated into physical queue addresses for accessing the corresponding hardware queue manager. The virtual queues can be moved from one physical queue in one hardware queue manager to a different physical queue in a different physical queue manager without changing the virtual address of the virtual queue.

公开(公告)号：US20190042305A1

公开(公告)日：2019-02-07

申请号：US15912746

申请日：2018-03-06

Applicant: Intel Corporation

Inventor： Niall D. McDonnell ,  Debra Bernstein ,  Patrick Fleming ,  Chris Macnamara ,  Andrew Cunningham ,  Bruce Richardson ,  Brendan N. Ryan

IPC: G06F9/48 ,  G06F9/50

Abstract: Technologies for moving workloads between hardware queue managers include a compute device. The compute device includes a set of hardware queue managers. Each hardware queue manager is to manage one or more queues of queue elements and each queue element is indicative of a data set to be operated on by a thread. The compute device also includes circuitry to execute a workload with a first hardware queue manager of the set of hardware queue managers, determine whether a workload migration condition is present, determine whether a second hardware queue manager of the set of hardware queue managers has sufficient capacity to manage a set of queues associated with the workload, move, in response to a determination that the second hardware queue manager does have sufficient capacity, the workload to the second hardware queue manager, and reduce, after the move of the workload to the second hardware queue manager, a power usage of the first hardware queue manager.

公开(公告)号：US09830285B2

公开(公告)日：2017-11-28

申请号：US14882867

申请日：2015-10-14

Applicant: Intel Corporation

Inventor： Gilbert Wolrich ,  Debra Bernstein ,  Daniel Cutter ,  Christopher Dolan ,  Matthew J. Adiletta

IPC: G06F13/20 ,  G06F12/0806 ,  G06F12/06 ,  G06F12/02 ,  G06F3/06 ,  G06F13/28 ,  G06F13/40 ,  G06F15/76 ,  G06F15/173 ,  G11C7/10 ,  G06F12/10 ,  G06F12/109

CPC classification number: G06F13/20 ,  G06F3/0622 ,  G06F3/0661 ,  G06F3/0679 ,  G06F12/0223 ,  G06F12/0284 ,  G06F12/06 ,  G06F12/0806 ,  G06F12/10 ,  G06F12/109 ,  G06F13/28 ,  G06F13/4027 ,  G06F15/17318 ,  G06F15/76 ,  G06F2212/1041 ,  G06F2212/206 ,  G06F2212/251 ,  G11C7/1033 ,  G11C7/1072

Abstract: The disclosure includes, in general, among other aspects, an apparatus having multiple programmable units integrated within a processor. The apparatus has circuitry to map addresses in a single address space to resources within the multiple programmable units where the single address space includes addresses for different ones of the resources in different ones of the multiple programmable units and where there is a one-to-one correspondence between respective addresses in the single address space and resources within the multiple programmable units.

公开(公告)号：US09824038B2

公开(公告)日：2017-11-21

申请号：US14882897

申请日：2015-10-14

Applicant: Intel Corporation

Inventor： Gilbert Wolrich ,  Debra Bernstein ,  Daniel Cutter ,  Christopher Dolan ,  Matthew J. Adiletta

IPC: G06F13/20 ,  G06F12/0806 ,  G06F12/06 ,  G06F12/02 ,  G06F3/06 ,  G06F13/28 ,  G06F13/40 ,  G06F15/76 ,  G06F15/173 ,  G11C7/10 ,  G06F12/10 ,  G06F12/109

CPC classification number: G06F13/20 ,  G06F3/0622 ,  G06F3/0661 ,  G06F3/0679 ,  G06F12/0223 ,  G06F12/0284 ,  G06F12/06 ,  G06F12/0806 ,  G06F12/10 ,  G06F12/109 ,  G06F13/28 ,  G06F13/4027 ,  G06F15/17318 ,  G06F15/76 ,  G06F2212/1041 ,  G06F2212/206 ,  G06F2212/251 ,  G11C7/1033 ,  G11C7/1072

Abstract: The disclosure includes, in general, among other aspects, an apparatus having multiple programmable units integrated within a processor. The apparatus has circuitry to map addresses in a single address space to resources within the multiple programmable units where the single address space includes addresses for different ones of the resources in different ones of the multiple programmable units and where there is a one-to-one correspondence between respective addresses in the single address space and resources within the multiple programmable units.

公开(公告)号：US09535860B2

公开(公告)日：2017-01-03

申请号：US13743795

申请日：2013-01-17

Applicant: Intel Corporation

Inventor： Daniel F. Cutter ,  Blaise Fanning ,  Ramadass Nagarajan ,  Jose S. Niell ,  Debra Bernstein ,  Deepak Limaye ,  Ioannis T. Schoinas ,  Ravishankar Iyer

IPC: G06F12/00 ,  G06F13/16

CPC classification number: G06F13/1663 ,  G06F13/1605 ,  G06F13/161 ,  G06F2212/1024 ,  G06F2213/0064 ,  Y02D10/14

Abstract: In an embodiment, a shared memory fabric is configured to receive memory requests from multiple agents, where at least some of the requests have an associated deadline value to indicate a maximum latency prior to completion of the memory request. Responsive to the requests, the fabric is to arbitrate between the requests based at least in part on the deadline values. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，共享存储器结构被配置为从多个代理接收存储器请求，其中至少一些请求具有关联的最终期限值，以在完成存储器请求之前指示最大等待时间。 响应于请求，结构是至少部分地基于期限值来在请求之间进行仲裁。 描述和要求保护其他实施例。

公开(公告)号：US09128818B2

公开(公告)日：2015-09-08

申请号：US14286055

申请日：2014-05-23

Applicant: Intel Corporation

Inventor： Gilbert Wolrich ,  Debra Bernstein ,  Daniel Cutter ,  Christopher Dolan ,  Matthew J. Adiletta

IPC: G06F12/00 ,  G06F12/02 ,  G06F12/10

CPC classification number: G06F13/20 ,  G06F3/0622 ,  G06F3/0661 ,  G06F3/0679 ,  G06F12/0223 ,  G06F12/0284 ,  G06F12/06 ,  G06F12/0806 ,  G06F12/10 ,  G06F12/109 ,  G06F13/28 ,  G06F13/4027 ,  G06F15/17318 ,  G06F15/76 ,  G06F2212/1041 ,  G06F2212/206 ,  G06F2212/251 ,  G11C7/1033 ,  G11C7/1072

Abstract: The disclosure includes, in general, among other aspects, an apparatus having multiple programmable units integrated within a processor. The apparatus has circuitry to map addresses in a single address space to resources within the multiple programmable units where the single address space includes addresses for different ones of the resources in different ones of the multiple programmable units and where there is a one-to-one correspondence between respective addresses in the single address space and resources within the multiple programmable units.

Abstract translation: 一般来说，本公开包括具有集成在处理器内的多个可编程单元的装置。 该装置具有将单个地址空间中的地址映射到多个可编程单元内的资源的电路，其中单个地址空间包括针对多个可编程单元中的不同可编程单元中的不同资源的地址，并且其中存在一对一 单个地址空间中的各个地址与多个可编程单元内的资源之间的对应关系。