公开(公告)号：US20200286847A1

公开(公告)日：2020-09-10

申请号：US16646084

申请日：2018-01-12

Applicant: Intel Corporation

Inventor： Changhua LIU ,  Xiaoying GUO ,  Aleksandar ALEKSOV ,  Steve S. CHO ,  Leonel ARANA ,  Robert MAY ,  Gang DUAN

IPC: H01L23/00

Abstract: A patch structure of an integrated circuit package comprises a core having a first side facing downwards and a second side facing upwards. Forming a first solder resist (SR) layer on the first side of the core, wherein the first SR layer comprises a first layer interconnect (FLI) and has a first set of one or more microbumps thereon to bond to one or more logic die. Forming a second solder resist (SR) layer on the second side of the core, wherein the second SR layer has a second set of one or more microbumps thereon to bond with a substrate. One or more bridge dies includes a respective sets of bumps, wherein the one or more bridge dies is disposed flipped over within the core such that the respective sets of bumps face downward and connect to the first set of one or more microbumps in the FLI.

公开(公告)号：US20200258800A1

公开(公告)日：2020-08-13

申请号：US16274091

申请日：2019-02-12

Applicant: Intel Corporation

Inventor： Jeremy ECTON ,  Oscar OJEDA ,  Leonel ARANA ,  Suddhasattwa NAD ,  Robert MAY ,  Hiroki TANAKA ,  Brandon C. MARIN

IPC: H01L23/31 ,  H05K1/02 ,  H05K3/06 ,  H01L21/283

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, the electronic package comprises a substrate and a conductive feature over the substrate. In an embodiment, a metallic mask is positioned over the conductive feature. In an embodiment, the metallic mask extends beyond a first edge of the conductive feature and a second edge of the conductive feature.