公开(公告)号：US20220012062A1

公开(公告)日：2022-01-13

申请号：US17482201

申请日：2021-09-22

Applicant: Intel Corporation

Inventor： Subrata Banik ,  Rajaram Regupathy ,  Vincent Zimmer ,  Julius Mandelblat

IPC: G06F9/4401 ,  G06F11/34

Abstract: Methods, apparatus, systems, and articles of manufacture to increase boot performance are disclosed. An example apparatus including instructions stored in the apparatus; and processor circuitry to execute the instructions to: during a boot process: identify a boot task that is to be performed during the boot process; execute the boot task using a first processor component; collect data corresponding to the execution of the boot task on the first processor component; categorize the boot task based on the collected data; and generate an entry for a boot table based on the categorization, the boot table used to schedule the boot task on at least one of the first processor component or a second processor component different than the first processor component based on the categorization.

公开(公告)号：US20210089326A1

公开(公告)日：2021-03-25

申请号：US17111989

申请日：2020-12-04

Applicant: Intel Corporation

Inventor： Subrata Banik ,  Rajaram Regupathy ,  Kalyan Kondapally

IPC: G06F9/4401 ,  G06F9/451 ,  G06F1/3212 ,  G06F15/78 ,  G06F11/30

Abstract: Systems, apparatuses and methods may provide for technology that detects a low battery condition in a computing system including an integrated graphics processor and a discrete graphics processor, wherein the low battery condition is detected during a pre-boot stage of the computing system. The technology may also disable a root port associated with the discrete graphics processor in response to the low battery condition, conduct an initialization of an integrated display while the root port is disabled, and enable the root port in response to a successful negotiation of increased power by a verified read write code of an embedded controller of the computing system.

公开(公告)号：US20210019420A1

公开(公告)日：2021-01-21

申请号：US17032369

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Rajaram Regupathy ,  Subrata Banik ,  Vincent Zimmer ,  Saranya Gopal

IPC: G06F21/57 ,  G06F21/79 ,  G06F9/48 ,  G06F9/54

Abstract: Embodiments are directed to a phased boot process to dynamically initialize devices in a verified environment. An embodiment of a system includes a memory device to store platform initialization firmware to cause the processing system to: initialize, during a boot process, a portion of the one or more memory modules as system management random access memory (SMRAM) for system management mode (SMM) usage; generate an SMM component in the SMRAM, the SMM component comprising an SMM handler routine to handle dynamic intellectual property (IP) management operations corresponding to the plurality of hardware components; register the SMM handler routine with an SMM interrupt (SMI) for identification of SMM events from an operating system (OS); and generate an SMM dispatcher in the SMRAM, the SMM dispatcher to create an instance of the SMM handler routine in the SMRAM in response to receiving an SMI from the OS during runtime of the processing system.

公开(公告)号：US12073225B2

公开(公告)日：2024-08-27

申请号：US17097055

申请日：2020-11-13

Applicant: Intel Corporation

Inventor： Subrata Banik ,  Asad Azam ,  Vincent James Zimmer ,  Rajaram Regupathy

IPC: G06F9/4401 ,  G06F3/06 ,  G06F13/16

CPC classification number: G06F9/4403 ,  G06F3/0611 ,  G06F3/0659 ,  G06F3/068 ,  G06F13/1668

Abstract: A data processing system comprises a processing core to execute a basic input/output system (BIOS) as part of a boot process. The data processing system also comprises static random-access memory (SRAM) in communication with the processing core. The data processing system also comprises a pre-BIOS component in communication with the SRAM. The pre-BIOS component is configured to execute a pre-BIOS block before the processing core begins executing the BIOS. The pre-BIOS block, when executed by the pre-BIOS component, causes the pre-BIOS component to (a) initialize the pre-BIOS component, (b) measure an amount of time taken to initialize the pre-BIOS component, and (c) save the measured amount of time to the SRAM as a pre-BIOS boot-time record. Other embodiments are described and claimed.

公开(公告)号：US12063280B2

公开(公告)日：2024-08-13

申请号：US18456102

申请日：2023-08-25

Applicant: Intel Corporation

Inventor： Rajesh Poornachandran ,  Vincent Zimmer ,  Subrata Banik ,  Marcos Carranza ,  Kshitij Arun Doshi ,  Francesc Guim Bernat ,  Karthik Kumar

IPC: H04L67/51 ,  H04L9/00 ,  H04L9/32 ,  H04L41/5009 ,  H04L67/562

CPC classification number: H04L67/51 ,  H04L9/3278 ,  H04L41/5009 ,  H04L67/562 ,  H04L9/50

Abstract: An apparatus to facilitate provenance audit trails for microservices architectures is disclosed. The apparatus includes one or more processors to obtain provenance metadata for a microservice from a local blockchain of provenance metadata maintained for the hardware resource executing a task performed by the microservice, the provenance metadata comprising identification of the microservice, operating state of at least one of a hardware resource or a software resource used to execute the microservice and the task, and an operating state of a sidecar of the microservice during the task; access one or more policies established for the microservice; analyze the provenance metadata with respect to the one or more policies to identify if there is a violation of the one or more policies; and generate one or more evaluation metrics based on whether the violation of the one or more policies is identified.

公开(公告)号：US11941409B2

公开(公告)日：2024-03-26

申请号：US16914331

申请日：2020-06-27

Applicant: Intel Corporation

Inventor： Subrata Banik ,  Asad Azam ,  Jenny M. Pelner ,  Vincent Zimmer ,  Rajaram Regupathy

IPC: G06F9/44 ,  G06F9/4401

CPC classification number: G06F9/4403 ,  G06F2212/60

Abstract: Systems, methods, and apparatuses relating to circuitry to implement a multiprocessor boot flow for a faster boot process are described. In one embodiment, a system includes a hardware processor comprising a processor core, a cache coupled to the hardware processor, storage for hardware initialization code, and a controller circuit to initialize a portion of the cache as memory for usage by the hardware initialization code before beginning execution of the hardware initialization code after a power on of the system.

公开(公告)号：US11870669B2

公开(公告)日：2024-01-09

申请号：US17556051

申请日：2021-12-20

Applicant: Intel Corporation

Inventor： Rajesh Poornachandran ,  Vincent Zimmer ,  Subrata Banik ,  Marcos Carranza ,  Kshitij Arun Doshi ,  Francesc Guim Bernat ,  Karthik Kumar

IPC: H04L43/0817 ,  H04L43/0894 ,  G06N20/00 ,  H04L41/5009 ,  H04L43/0864

CPC classification number: H04L43/0817 ,  G06N20/00 ,  H04L41/5009 ,  H04L43/0864 ,  H04L43/0894

Abstract: An apparatus to facilitate at-scale telemetry using interactive matrix for deterministic microservices performance is disclosed. The apparatus includes one or more processors to: receive user input comprising an objective or task corresponding to scheduling a microservice for a service, wherein the objective or task may include QoS, SLO, ML feedback; identify interaction matrix components in an interaction matrix that match the objective or tasks for the microservice; identify knowledgebase components in knowledgebase that match the objective or tasks for the microservice; and determine a scheduling operation for the microservice, the scheduling operation to deploy the microservice in a configuration that is in accordance with the objective or task, wherein the configuration comprises a set of hardware devices and microservice interaction points determined based on the interaction matrix components and the knowledgebase components.

公开(公告)号：US11570264B1

公开(公告)日：2023-01-31

申请号：US17557604

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Rajesh Poornachandran ,  Vincent Zimmer ,  Subrata Banik ,  Marcos Carranza ,  Kshitij Arun Doshi ,  Francesc Guim Bernat ,  Karthik Kumar

IPC: H04L67/51 ,  H04L41/5009 ,  H04L9/32 ,  H04L67/562 ,  H04L9/00

Abstract: An apparatus to facilitate provenance audit trails for microservices architectures is disclosed. The apparatus includes one or more processors to: obtain, by a microservice of a service hosted in a datacenter, provisioned credentials for the microservice based on an attestation protocol; generate, for a task performed by the microservice, provenance metadata for the task, the provenance metadata including identification of the microservice, operating state of at least one of a hardware resource or a software resource used to execute the microservice and the task, and operating state of a sidecar of the microservice during the task; encrypt the provenance metadata with the provisioned credentials for the microservice; and record the encrypted provenance metadata in a local blockchain of provenance metadata maintained for the hardware resource executing the task and the microservice.

公开(公告)号：US20210081538A1

公开(公告)日：2021-03-18

申请号：US17109081

申请日：2020-12-01

Applicant: Intel Corporation

Inventor： Vincent Zimmer ,  Subrata Banik ,  Rajaram Regupathy

IPC: G06F21/57 ,  G06F21/54 ,  G06F21/79 ,  G06F9/4401 ,  G06F9/30 ,  G06F12/0811

Abstract: Systems, apparatuses and methods may provide for technology that initializes static random access memory (SRAM) of a processor in response to a reset of the processor, allocates the SRAM to one or more security enforcement operations, and triggers a multi-threaded execution of the one or more security enforcement operations before completion of a basic input output system (BIOS) phase. In one example, the multi-threaded execution is triggered independently of a dynamic RAM (DRAM) initialization.

公开(公告)号：US11989563B2

公开(公告)日：2024-05-21

申请号：US17111989

申请日：2020-12-04

Applicant: Intel Corporation

Inventor： Subrata Banik ,  Rajaram Regupathy ,  Kalyan Kondapally

IPC: G06F9/4401 ,  G06F1/26 ,  G06F1/3212 ,  G06F9/451 ,  G06F11/30 ,  G06F15/78

CPC classification number: G06F9/4406 ,  G06F1/3212 ,  G06F9/4403 ,  G06F9/451 ,  G06F11/3013 ,  G06F11/3062 ,  G06F15/7807

Abstract: Systems, apparatuses and methods may provide for technology that detects a low battery condition in a computing system including an integrated graphics processor and a discrete graphics processor, wherein the low battery condition is detected during a pre-boot stage of the computing system. The technology may also disable a root port associated with the discrete graphics processor in response to the low battery condition, conduct an initialization of an integrated display while the root port is disabled, and enable the root port in response to a successful negotiation of increased power by a verified read write code of an embedded controller of the computing system.