公开(公告)号：US20200312768A1

公开(公告)日：2020-10-01

申请号：US16366647

申请日：2019-03-27

Applicant: Intel Corporation

Inventor： Suddhasattwa NAD ,  Rahul MANEPALLI ,  Srinivas PIETAMBARAM ,  Marcel WALL

IPC: H01L23/538 ,  H01L23/498 ,  H01L25/18 ,  H01L21/48

Abstract: An interconnection structure is disclosed. The interconnection structure includes a dielectric layer, an interfacial TiC layer on the dielectric layer, the interfacial TiC layer having a uniform thickness, and a Ti layer on the TiC layer.

公开(公告)号：US20200258800A1

公开(公告)日：2020-08-13

申请号：US16274091

申请日：2019-02-12

Applicant: Intel Corporation

Inventor： Jeremy ECTON ,  Oscar OJEDA ,  Leonel ARANA ,  Suddhasattwa NAD ,  Robert MAY ,  Hiroki TANAKA ,  Brandon C. MARIN

IPC: H01L23/31 ,  H05K1/02 ,  H05K3/06 ,  H01L21/283

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, the electronic package comprises a substrate and a conductive feature over the substrate. In an embodiment, a metallic mask is positioned over the conductive feature. In an embodiment, the metallic mask extends beyond a first edge of the conductive feature and a second edge of the conductive feature.

公开(公告)号：US20190320537A1

公开(公告)日：2019-10-17

申请号：US15954040

申请日：2018-04-16

Applicant: Intel Corporation

Inventor： Suddhasattwa NAD ,  Rahul MANEPALLI ,  Marcel WALL

IPC: H05K3/38 ,  H01L21/027 ,  H01L21/48 ,  H01L23/498 ,  H05K1/03

Abstract: Embodiments described herein are directed to interfacial layers and techniques of forming such interfacial layers. An interfacial layer having one or more light absorbing molecules is on a metal layer. The light absorbing molecule(s) may comprise a moiety exhibiting light absorbing properties. The interfacial layer can assist with improving adhesion of a resist layer to the metal layer and with improving use of one or more lithography techniques to fabricate interconnects and/or features using the resist and metal layers for a package substrate, a semiconductor package, or a PCB. For one embodiment, the interfacial layer includes, but is not limited to, an organic interfacial layer. Examples of organic interfacial layers include, but are not limited to, self-assembled monolayers (SAMs), constructs and/or variations of SAMs, organic adhesion promotor moieties, and non-adhesion promoter moieties.

公开(公告)号：US20240312853A1

公开(公告)日：2024-09-19

申请号：US18121331

申请日：2023-03-14

Applicant: Intel Corporation

Inventor： Sashi S. KANDANUR ,  Srinivas V. PIETAMBARAM ,  Darko GRUJICIC ,  Brandon C. MARIN ,  Suddhasattwa NAD ,  Benjamin DUONG ,  Gang DUAN ,  Mohammad Mamunur RAHMAN ,  Numair AHMED

IPC: H01L23/15 ,  H01L23/498

CPC classification number: H01L23/15 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838

Abstract: Embodiments herein relate to systems, apparatuses, techniques and/or processes for creating a substrate out of a plurality of layers of glass, where the substrate includes one or more vias that extend through each of the plurality of layers of glass. In embodiments, a high aspect ratio via may be constructed through the substrate by electrically coupling the individual vias. Other embodiments may be described and/or claimed.

公开(公告)号：US20240213301A1

公开(公告)日：2024-06-27

申请号：US18089471

申请日：2022-12-27

Applicant: Intel Corporation

Inventor： Darko GRUJICIC ,  Thomas L. SOUNART ,  Benjamin DUONG ,  Kristof DARMAWIKARTA ,  Shayan KAVIANI ,  Suddhasattwa NAD ,  Mahdi MOHAMMADIGHALENI ,  Marcel WALL ,  Rengarajan SHANMUGAM

IPC: H01G4/33

CPC classification number: H01L28/40 ,  H01G4/33

Abstract: Embodiments disclosed herein include a package core. In an embodiment, the package core comprises a core substrate that includes glass. In an embodiment, a cavity is provided into the core substrate. In an embodiment, a capacitor is lining sidewalls of the cavity, and the capacitor comprises a first layer, a dielectric layer over the first layer, and a second layer over the dielectric layer.

公开(公告)号：US20240213132A1

公开(公告)日：2024-06-27

申请号：US18089476

申请日：2022-12-27

Applicant: Intel Corporation

Inventor： Kristof DARMAWIKARTA ,  Benjamin DUONG ,  Darko GRUJICIC ,  Shayan KAVIANI ,  Mahdi MOHAMMADIGHALENI ,  Suddhasattwa NAD ,  Thomas L. SOUNART ,  Marcel WALL ,  Ravindranath V. MAHAJAN ,  Rahul N. MANEPALLI

IPC: H01L23/498 ,  H01L27/01

CPC classification number: H01L23/49838 ,  H01L27/016 ,  H01L28/86 ,  H01L28/90 ,  H01L23/49822 ,  H01L23/49894 ,  H01L24/16

Abstract: Embodiments disclosed herein include an electronic package. In an embodiment, the electronic package comprises a package substrate, where the package substrate comprises a plurality of stacked dielectric layers. In an embodiment, the electronic package further comprises an opening into the package substrate, where the opening passes through at least two of the plurality of dielectric layers. In an embodiment, a first pad is at the bottom of the opening, a capacitor is disposed in the opening, and a second pad is over the capacitor.

公开(公告)号：US20240177918A1

公开(公告)日：2024-05-30

申请号：US18071237

申请日：2022-11-29

Applicant: Intel Corporation

Inventor： Suddhasattwa NAD ,  Brandon C. MARIN ,  Jeremy D. ECTON ,  Srinivas V. PIETAMBARAM ,  Gang DUAN ,  Mohammad Mamunur RAHMAN

IPC: H01F27/28 ,  H01F27/30 ,  H01F41/04 ,  H01L23/08 ,  H01L23/31

CPC classification number: H01F27/2804 ,  H01F27/306 ,  H01F41/041 ,  H01L23/08 ,  H01L23/3128 ,  H01F2027/2809 ,  H01F2027/2819

Abstract: Embodiments disclosed herein include a package core. In an embodiment, the package core comprises a core substrate, a first opening through the core substrate, a second opening through the core substrate and adjacent to the first opening, and a first structure around the core substrate between the first opening and the second opening. In an embodiment, the first structure is electrically conductive. The package core may further comprise a second structure around the core substrate outside of the first opening and the second opening, where the second structure is electrically conductive.

公开(公告)号：US20240063069A1

公开(公告)日：2024-02-22

申请号：US17892930

申请日：2022-08-22

Applicant: Intel Corporation

Inventor： Brandon C. MARIN ,  Rahul N. MANEPALLI ,  Ravindranath V. MAHAJAN ,  Srinivas V. PIETAMBARAM ,  Jeremy D. ECTON ,  Gang DUAN ,  Suddhasattwa NAD

IPC: H01L23/13 ,  H01L23/498 ,  H01L23/15

CPC classification number: H01L23/13 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/15 ,  H01L24/16

Abstract: Embodiments disclosed herein include package substrates with glass cores. In an embodiment, a core comprises a substrate with a first surface and a second surface opposite from the first surface. In an embodiment, the substrate comprises glass, In an embodiment, through glass vias (TGVs) pass through the substrate, and notches are formed into the first surface and the second surface of the substrate.

公开(公告)号：US20240006297A1

公开(公告)日：2024-01-04

申请号：US17853582

申请日：2022-06-29

Applicant: Intel Corporation

Inventor： Suddhasattwa NAD ,  Kristof DARMAWIKARTA ,  Srinivas V. PIETAMBARAM ,  Tarek A. IBRAHIM ,  Rahul N. MANEPALLI ,  Darko GRUJICIC ,  Marcel WALL ,  Yi YANG

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/538

CPC classification number: H01L23/49894 ,  H01L21/4846 ,  H01L23/538 ,  H01L21/481

Abstract: Embodiments herein relate to systems, apparatuses, or processes for forming a silicide and a silicon nitrate layer between a copper feature and dielectric to reduce delamination of the dielectric. Embodiments allow an unroughened surface for the copper feature to reduce the insertion loss for transmission lines that go through the unroughened surface of the copper. Embodiments may include sequential interlayers between a dielectric and copper. Other embodiments may be described and/or claimed.

公开(公告)号：US20230317584A1

公开(公告)日：2023-10-05

申请号：US17707371

申请日：2022-03-29

Applicant: Intel Corporation

Inventor： Yi YANG ,  Suddhasattwa NAD ,  Marcel WALL ,  Rahul N. MANEPALLI ,  Benjamin DUONG

IPC: H01L23/498 ,  H01L21/48 ,  H05K1/18

CPC classification number: H01L23/49822 ,  H01L23/49866 ,  H01L23/49894 ,  H01L21/4857 ,  H01L21/486 ,  H05K1/181 ,  H01L24/16

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a package substrate with a plurality of first layers, where the first layers comprise an organic material. In an embodiment, a trace is embedded in the package substrate. In an embodiment, a second layer is over the trace, where the second layer comprises silicon and nitrogen, and wherein the second layer is chemically bonded to one of the first layers by an oxygen containing ligand and/or a nitrogen containing ligand.