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    ADAPTIVE DYNAMIC DISPATCH OF MICRO-OPERATIONS
    12.
    发明公开
    ADAPTIVE DYNAMIC DISPATCH OF MICRO-OPERATIONS 审中-公开

    公开(公告)号：US20230205538A1

    公开(公告)日：2023-06-29

    申请号：US17561394

    申请日：2021-12-23

    Applicant: Intel Corporation

    Inventor： Or Beit Aharon ,  Zeev Sperber ,  Gavri Berger ,  Amit Gradstein ,  Nofar Hasson

    IPC: G06F9/38 ,  G06F9/30

    CPC classification number: G06F9/3836 ,  G06F9/30145 ,  G06F9/3001

    Abstract: Embodiments of apparatuses, methods, and systems for adaptive dynamic dispatch of micro-operations are disclosed. In an embodiment, an apparatus includes a plurality of redundant execution units, a dispatcher, control hardware, a first counter, and a second counter. The dispatcher is to dispatch micro-operations to one or more of the plurality of redundant execution units, the micro-operations having a plurality of micro-operation types. The first counter to generate a first count of dispatches, during a window, of micro-operations having a first type of the plurality of micro-operation types. The second counter to generate a second count of dispatches, during the window, of micro-operations having any type of the plurality of micro-operation types. The control hardware is to cause a switch between a first mode and a second mode based in part on the first count and the second count. In the first mode, the dispatcher is to dispatch micro-operations having the first type to only a subset of the plurality of redundant execution units. In the second mode, the dispatcher is to dispatch micro-operations having the first type to all of the plurality of redundant execution units.

    SYSTEMS, APPARATUSES, AND METHODS FOR ADDITION OF PARTIAL PRODUCTS
    14.
    发明申请
    SYSTEMS, APPARATUSES, AND METHODS FOR ADDITION OF PARTIAL PRODUCTS 有权

    公开(公告)号：US20230048998A1

    公开(公告)日：2023-02-16

    申请号：US17964964

    申请日：2022-10-13

    Applicant: Intel Corporation

    Inventor： Robert Valentine ,  Galina Ryvchin ,  Piotr Majcher ,  Mark J. Charney ,  Elmoustapha Ould-Ahmed-Vall ,  Jesus Corbal ,  Milind B. Girkar ,  Zeev Sperber ,  Simon Rubanovich ,  Amit Gradstein

    IPC: G06F9/30 ,  G06F7/544 ,  G06F9/38

    Abstract: Embodiments of systems, apparatuses, and methods for fused multiple add. In some embodiments, a decoder decodes a single instruction having an opcode, a destination field representing a destination operand, and fields for a first, second, and third packed data source operand, wherein packed data elements of the first and second packed data source operand are of a first, different size than a second size of packed data elements of the third packed data operand. Execution circuitry then executes the decoded single instruction to perform, for each packed data element position of the destination operand, a multiplication of a M N-sized packed data elements from the first and second packed data sources that correspond to a packed data element position of the third packed data source, add of results from these multiplications to a full-sized packed data element of a packed data element position of the third packed data source, and storage of the addition result in a packed data element position destination corresponding to the packed data element position of the third packed data source, wherein M is equal to the full-sized packed data element divided by N.

    Systems and methods to perform floating-point addition with selected rounding
    18.
    发明授权
    Systems and methods to perform floating-point addition with selected rounding 有权

    公开(公告)号：US11175891B2

    公开(公告)日：2021-11-16

    申请号：US16370966

    申请日：2019-03-30

    Applicant: Intel Corporation

    Inventor： Simon Rubanovich ,  Amit Gradstein ,  Zeev Sperber ,  Mrinmay Dutta

    IPC: G06F7/499 ,  G06F7/483 ,  G06F9/38 ,  G06F17/16

    Abstract: Disclosed embodiments relate to performing floating-point addition with selected rounding. In one example, a processor includes circuitry to decode and execute an instruction specifying locations of first and second floating-point (FP) sources, and an opcode indicating the processor is to: bring the FP sources into alignment by shifting a mantissa of the smaller source FP operand to the right by a difference between their exponents, generating rounding controls based on any bits that escape; simultaneously generate a sum of the FP sources and of the FP sources plus one, the sums having a fuzzy-Jbit format having an additional Jbit into which a carry-out, if any, select one of the sums based on the rounding controls, and generate a result comprising a mantissa-wide number of most-significant bits of the selected sum, starting with the most significant non-zero Jbit.

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