Abstract:
Disclosed is a method for printing a media sheet in a media processing device. The method includes aligning a first portion of a printhead of the media processing device to a print area of the media sheet. The method further includes printing the print area of the media sheet by traversing the printhead over the print area in a first direction. The printing is performed by the first portion. Further, the method includes aligning a second portion of the printhead to the print area by adjusting the media sheet relative to the printhead by an index distance in a direction perpendicular to the first direction. Thereafter, the method includes reprinting the print area by traversing the printhead over the print area in a second direction opposite to the first direction. The reprinting is performed by the second portion.
Abstract:
A method of transforming a n-bit data packet to a m-bit data packet with a lookup table. The lookup table includes at least one entry data packet and at least one respective delta value associated with each entry data packet. The method includes the acts of receiving an input data packet having n-bits, indexing the lookup table with at least a portion of the input data packet to obtain one of the at least one entry data packet, and decompressing the obtained entry data packet with the at least one respective delta value associated with the obtained entry data packet, thereby resulting in an output data packet having m-bits. The decompressing act includes using a portion of the input data packet to determine the number of delta values called for decompressing the obtained entry data packet. The method can be used in, for example, an image processor.
Abstract:
A method for performing a division operation in a system includes a) determining an approximate quotient of a numerator value and a denominator value; b) determining an initial error of the approximate quotient; c) determining a quotient adjustment value based on the initial error; d) determining whether to apply the quotient adjustment value to the approximate quotient; e) if the determination at d) is YES, then applying the quotient adjustment value to the approximate quotient; f) determining an iterative error of the approximate quotient; g) updating the quotient adjustment value based on the iterative error; h) repeating acts d) through g) until the determination at d) is NO, thereby determining a final value for the approximate quotient; i) generating an integer quotient based on the final value of the approximate quotient; and j) using the integer quotient with regard to at least one aspect of the system.
Abstract:
An integrated circuit including a logic analyzer with enhanced analyzing and debugging capabilities and a method therefor. In one embodiment of the present invention, an embedded logic analyzer (ELA) receives a plurality of signals from a plurality of buses within an integrated circuit (IC). The ELA includes an interconnect module to select a trigger signal and/or a sampled signal from the plurality of received signals. A trigger module sets at least one trigger condition and detects if the trigger signal satisfies the at least one trigger condition. When the trigger condition is satisfied, an output module performs at least one task based upon the satisfied at least one trigger condition. If a sampling process is initiated by the output module, the plurality of sampled signals is sampled and may be stored in a memory. The capability of the output module to perform multiple user-defined tasks enhances the debugging capability of the ELA and makes it more versatile.
Abstract:
A system for testing or debugging a system including the integrated circuit having an embedded logic analyzer. In one embodiment, the system includes a computing device coupled to the logic analyzer for receiving the at least one output. A user interface run on the computing device assigns an attribute to at least one signal associated with the logic analyzer, determines a new signal or value not provided by the logic analyzer, the new signal or value being based upon the at least one signal as received from the logic analyzer and upon a predetermined definition, and presents the new signal or value to a system user.
Abstract:
Disclosed is a method for printing a media sheet in a media processing device. The method includes aligning a first portion of a printhead of the media processing device to a print area of the media sheet. The method further includes printing the print area of the media sheet by traversing the printhead over the print area in a first direction. The printing is performed by the first portion. Further, the method includes aligning a second portion of the printhead to the print area by adjusting the media sheet relative to the printhead by an index distance in a direction perpendicular to the first direction. Thereafter, the method includes reprinting the print area by traversing the printhead over the print area in a second direction opposite to the first direction. The reprinting is performed by the second portion.
Abstract:
A method and an imaging apparatus for reducing print grain effect in an image to be printed by a printing device are disclosed. One or more flat field areas, each comprising at least one flat field pixel, are detected in the image. A color value of each detected flat field pixel in the one or more flat field areas is modified using a unique flat field optimized color lookup table. The modification of the color value of each flat field pixel in the image reduces the print grain effect in the image to be printed by the printing device.
Abstract:
An application specific integrated circuit (ASIC) is configured to perform image processing tasks on a printer or other multi-function device. The ASIC includes a processor, a dedicated cache memory, a cache controller and additional Static Random Access Memory (SRAM) normally employed in image processing tasks. This additional SRAM may be dynamically allocated as a cache memory when not otherwise occupied.
Abstract:
Digital images that are produced by an image forming device may be processed using an edge enhancement technique to reduce the effects of halftone color depth reductions. For each element in the original image, certain detail elements are classified by examining the magnitude of pixel intensity gradients between elements of interest in a first window applied at each element and other elements in the first window. If a first predetermined condition is satisfied, those elements locations are stored. After halftoning, a morphological filter may be applied to the same element locations in the halftone image to enhance the halftone image.
Abstract:
A system for testing or debugging a device under test having an embedded logic analyzer. In one embodiment, the system includes software stored in non-transitory memory for testing a device under test having an embedded logic analyzer, the software program product having instructions which, when executed by a computing device associated with the device under test cause the computing device to reconstruct signals of interest in the device under test based at least in part upon signals captured by the embedded logic analyzer during the test or debug session, and cause the computing device to display the reconstructed signals of interest to a user of the computing device.