公开(公告)号：US10885314B2

公开(公告)日：2021-01-05

申请号：US15876217

申请日：2018-01-22

Applicant: Kneron Inc.

Inventor： Chun-Chen Liu

IPC: G06K9/00 ,  G06K9/66

Abstract: A face identification system includes a transmitter, a receiver, a database, an artificial intelligence chip, and a main processor. The transmitter is used for emitting at least one first light signal to an object. The receiver is used for receiving at least one second light signal reflected by the object. The database is used for saving training data. The artificial intelligence chip is coupled to the transmitter, the receiver, and the database for identifying a face image from the object according to the at least one second light signal and the training data. The main processor is coupled to the artificial intelligence chip for receiving a face identification signal generated from the artificial intelligence chip.

公开(公告)号：US10552732B2

公开(公告)日：2020-02-04

申请号：US15242610

申请日：2016-08-22

Applicant: Kneron Inc.

Inventor： Yilei Li ,  Yuan Du ,  Chun-Chen Liu ,  Li Du

IPC: G06N3/063

Abstract: A multi-layer artificial neural network having at least one high-speed communication interface and N computational layers is provided. N is an integer larger than 1. The N computational layers are serially connected via the at least one high-speed communication interface. Each of the N computational layers respectively includes a computation circuit and a local memory. The local memory is configured to store input data and learnable parameters for the computation circuit. The computation circuit in the ith computational layer provides its computation results, via the at least one high-speed communication interface, to the local memory in the (i+1)th computational layer as the input data for the computation circuit in the (i+1)th computational layer, wherein i is an integer index ranging from 1 to (N−1).

公开(公告)号：US20180053086A1

公开(公告)日：2018-02-22

申请号：US15243907

申请日：2016-08-22

Applicant: Kneron Inc.

Inventor： Chun-Chen Liu ,  Kangli Hao ,  Liu Liu

IPC: G06N3/063 ,  G06N3/04

CPC classification number: G06N3/063 ,  G06N3/0481

Abstract: A neural network including a controller and plural neurons is provided. The controller is configured to generate a forward propagation instruction in a computation process. Each neuron includes an instruction register, a storage device, and an application-specific computation circuit. The instruction register is configured to receive the forward propagation instruction from the controller and temporarily storing the forward propagation instruction. The storage device is configured to store at least one input and at least one learnable parameter. The application-specific computation circuit is invariably configured to dedicate to computations related to the neuron. In response to the forward propagation instruction received by the instruction register, the application-specific computation circuit is configured to perform a computation on the at least one input and the at least one learnable parameter according to an activation function and to feed back a computation result to the storage device.

公开(公告)号：US20180053084A1

公开(公告)日：2018-02-22

申请号：US15242610

申请日：2016-08-22

Applicant: Kneron Inc.

Inventor： Yilei Li ,  Yuan Du ,  Chun-Chen Liu ,  Li Du

IPC: G06N3/04 ,  G06N3/08

CPC classification number: G06N3/063 ,  G06N3/0454

Abstract: A multi-layer artificial neural network having at least one high-speed communication interface and N computational layers is provided. N is an integer larger than 1. The N computational layers are serially connected via the at least one high-speed communication interface. Each of the N computational layers respectively includes a computation circuit and a local memory. The local memory is configured to store input data and learnable parameters for the computation circuit. The computation circuit in the ith computational layer provides its computation results, via the at least one high-speed communication interface, to the local memory in the (i+1)th computational layer as the input data for the computation circuit in the (i+1)th computational layer, wherein i is an integer index ranging from 1 to (N−1).