公开(公告)号：US09195406B2

公开(公告)日：2015-11-24

申请号：US13930715

申请日：2013-06-28

Applicant: Micron Technology, Inc.

Inventor： Anthony R. Cabrera ,  Nicholas Hendrickson ,  Robert Melcher

IPC: G06F3/00 ,  G06F3/06

CPC classification number: G06F3/0604 ,  G06F3/0629 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0246 ,  G06F13/161 ,  G06F2212/7205

Abstract: Multiple segment operations having non-volatile state trackers in memory devices are disclosed. Operations are segmented in multiple segments and selectively performed to avoid violating timing requirements within a memory device. In at least one embodiment, a memory device operation is segmented into a plurality of segments and selectively performed within time frames of other memory device operations. Non-volatile state trackers maintain state values corresponding to each segment of multiple segmented operations.

Abstract translation: 公开了在存储器件中具有非易失性状态跟踪器的多段操作。 操作被分段在多个段中并且被选择性地执行以避免在存储器设备内违反时序要求。 在至少一个实施例中，存储器件操作被分割成多个段并且在其他存储器件操作的时间帧内选择性地执行。 非易失性状态跟踪器保持对应于多个分段操作的每个段的状态值。

公开(公告)号：US20150221384A1

公开(公告)日：2015-08-06

申请号：US14686092

申请日：2015-04-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Nicholas Hendrickson

IPC: G11C16/26

CPC classification number: G11C16/26 ,  G11C7/1033 ,  G11C7/1036 ,  G11C7/1039 ,  G11C7/106 ,  G11C11/5642 ,  G11C16/0458 ,  G11C16/0483 ,  G11C2207/2272 ,  G11C2211/5642

Abstract: Methods of operating a memory device include applying an increasing sense voltage to a plurality of memory cells, wherein memory cells of the plurality of memory cells each store data states representing two or more digits of data. The methods further include, in response to the increasing sense voltage reaching a particular level, initiating a transfer of data values of a particular digit of data for each memory cell of the plurality of memory cells while continuing to apply the increasing sense voltage to the plurality of memory cells.

Abstract translation: 操作存储器件的方法包括将增加的感测电压施加到多个存储器单元，其中多个存储器单元中的存储单元每个存储表示两位或多位数据的数据状态。 所述方法还包括响应于增加的感测电压达到特定水平，启动对多个存储器单元中的每个存储单元的特定数据数据的数据值的传送，同时继续将增加的感测电压施加到多个存储单元 的记忆细胞。

公开(公告)号：US20150213862A1

公开(公告)日：2015-07-30

申请号：US14674297

申请日：2015-03-31

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Nicholas Hendrickson

IPC: G11C8/10 ,  G11C11/408 ,  G11C11/4091

CPC classification number: G11C8/10 ,  G11C7/00 ,  G11C11/00 ,  G11C11/4087 ,  G11C11/4091 ,  G11C13/0026 ,  G11C16/06 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26

Abstract: Memories, and methods of operating such memories, having a memory cell, sense circuitry having a gate, program circuitry and a decoder having a first signal line connected to the gate of the sense circuitry, a second signal line connected to the program circuitry, and an output selectively connected to the memory cell. The decoder is configured to selectively connect the output to the first signal line responsive to a first control signal and to selectively connect the output to the second signal line responsive to the first control signal and a second control signal. The sense circuitry is configured to selectively activate the gate responsive to a third control signal.

Abstract translation: 存储器和操作这种存储器的方法，具有存储单元，具有栅极的感测电路，程序电路和具有连接到感测电路的栅极的第一信号线的解码器，连接到程序电路的第二信号线，以及 选择性地连接到存储单元的输出。 解码器被配置为响应于第一控制信号选择性地将输出连接到第一信号线，并且响应于第一控制信号和第二控制信号选择性地将输出连接到第二信号线。 感测电路被配置为响应于第三控制信号选择性地激活门。

公开(公告)号：US20140347947A1

公开(公告)日：2014-11-27

申请号：US14457039

申请日：2014-08-11

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Gerald Barkley ,  Nicholas Hendrickson

IPC: G11C5/14

CPC classification number: G11C5/147 ,  G11C5/14 ,  G11C8/08 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0069 ,  G11C16/08 ,  G11C16/3427

Abstract: An apparatus, such as a nonvolatile solid-state memory device, may, in some implementations, include access line bias circuitry to set a bias level associated with a deselected access line(s) of a memory core in response to mode information. In one approach, access line bias circuitry may use linear down regulation to change a voltage level on deselected access lines of a memory core. A memory access device, such as a host processor, may be provided that is capable of dynamically setting a mode of operation of a memory core of a memory device in order to manage power consumption of the memory. Other apparatuses and methods are also provided.

Abstract translation: 在一些实施方式中，诸如非易失性固态存储器件的装置可以包括存取线偏置电路，以响应于模式信息来设置与存储器芯的取消选择的存取线相关联的偏置电平。 在一种方法中，接入线偏置电路可以使用线性下调来改变存储器核心的取消选择的接入线路上的电压电平。 可以提供诸如主机处理器的存储器访问设备，其能够动态地设置存储器设备的存储器核心的操作模式，以便管理存储器的功耗。 还提供了其他装置和方法。

公开(公告)号：US20160005467A1

公开(公告)日：2016-01-07

申请号：US14856147

申请日：2015-09-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Nicholas Hendrickson

IPC: G11C16/06

CPC classification number: G11C16/06 ,  G11C7/10 ,  G11C7/109 ,  G11C7/22 ,  G11C8/06

Abstract: Methods of operating integrated circuit devices include logically combining an output signal indicating whether an operation is being performed with the logic level of a command signal line to generate a command signal to control circuitry of the integrated circuit device having the logic level of the command signal line when the output signal indicates that the operation is not being performed, and having a particular logic level when the output signal indicates that the operation is being performed. Integrated circuit devices include a command signal management circuit to provide a logic level of a particular command signal to control circuitry of the integrated circuit device when control signals indicate a desire to allow the particular command signal, and to provide a particular logic level to the control circuitry when the control signals indicate a desire to block the particular command signal.

Abstract translation: 操作集成电路装置的方法包括逻辑地组合指示是否正在执行操作与命令信号线的逻辑电平的输出信号以产生具有指令信号线的逻辑电平的集成电路装置的控制电路的命令信号 当输出信号指示操作未被执行时，并且当输出信号指示正在执行操作时具有特定的逻辑电平。 集成电路装置包括命令信号管理电路，用于当控制信号指示允许特定命令信号的期望并向控制器提供特定的逻辑电平时，向集成电路装置的控制电路提供特定命令信号的逻辑电平 当控制信号指示阻止特定命令信号的期望时，电路。

公开(公告)号：US20150262716A1

公开(公告)日：2015-09-17

申请号：US14700292

申请日：2015-04-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Nicholas Hendrickson

IPC: G11C29/00 ,  G11C16/14 ,  G11C16/28 ,  G11C16/08

CPC classification number: G11C29/70 ,  G06F11/1048 ,  G11C16/08 ,  G11C16/14 ,  G11C16/28 ,  G11C29/806 ,  G11C29/82

Abstract: Method of operating memory including storing and/or using an identifier indicating repair of a memory cell.

Abstract translation: 操作存储器的方法，包括存储和/或使用指示存储器单元的修复的标识符。

公开(公告)号：US20150235676A1

公开(公告)日：2015-08-20

申请号：US14703668

申请日：2015-05-04

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Gerald Barkley ,  Nicholas Hendrickson

IPC: G11C5/14

CPC classification number: G11C5/147 ,  G11C5/14 ,  G11C8/08 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0069 ,  G11C16/08 ,  G11C16/3427

Abstract: An apparatus, such as a nonvolatile solid-state memory device, may, in some implementations, include access line bias circuitry to set a bias level associated with a deselected access line(s) of a memory core in response to mode information. In one approach, access line bias circuitry may use linear down regulation to change a voltage level on deselected access lines of a memory core. A memory access device, such as a host processor, may be provided that is capable of dynamically setting a mode of operation of a memory core of a memory device in order to manage power consumption of the memory. Other apparatuses and methods are also provided.

Abstract translation: 在一些实施方式中，诸如非易失性固态存储器件的装置可以包括存取线偏置电路，以响应于模式信息来设置与存储器芯的取消选择的存取线相关联的偏置电平。 在一种方法中，接入线偏置电路可以使用线性下调来改变存储器核心的取消选择的接入线路上的电压电平。 可以提供诸如主机处理器的存储器访问设备，其能够动态地设置存储器设备的存储器核心的操作模式，以便管理存储器的功耗。 还提供了其他装置和方法。

公开(公告)号：US09025381B2

公开(公告)日：2015-05-05

申请号：US14148982

申请日：2014-01-07

Applicant: Micron Technology, Inc.

Inventor： Nicholas Hendrickson

IPC: G11C11/34 ,  G11C8/10 ,  G11C8/08 ,  G11C8/12

CPC classification number: G11C8/10 ,  G11C8/08 ,  G11C8/12

Abstract: Block-row decoders, memory block-row decoders, memories, methods for deselecting a decoder of a memory and methods of selecting a block of memory are disclosed. An example memory block-row decoder includes a plurality of block-row decoders, each of the block-row decoders having a decoder switch tree. Each block-row decoder is configured to bias a block select switch of the decoder switch tree with a first voltage while the block-row decoder is deselected and further configured to bias decoders switches of the decoder switch tree that are coupled to the block select switch with a second voltage while the block-row decoder is deselected, the second voltage less than the first voltage. An example method of deselecting a decoder of a memory includes providing decoder signals having different voltages to decoder switches from at least two different levels of a decoder switch tree while the decoder is deselected.

Abstract translation: 公开了块行解码器，存储器块行解码器，存储器，用于取消存储器解码器的方法和选择存储器块的方法。 示例性存储器块行解码器包括多个块行解码器，每个块行解码器具有解码器开关树。 每个块行解码器被配置为在块排解码器被取消选择的同时以第一电压偏置解码器开关树的块选择开关，并且还被配置为偏置解码器开关树的解码器开关，其耦合到块选择开关 在块排解码器被取消选择时具有第二电压，第二电压小于第一电压。 取消选择存储器的解码器的示例方法包括：在解码器被取消选择的同时，从解码器开关树的至少两个不同级别提供具有不同电压的解码器信号到解码器开关。

公开(公告)号：US09019762B2

公开(公告)日：2015-04-28

申请号：US14148256

申请日：2014-01-06

Applicant: Micron Technology, Inc.

Inventor： Nicholas Hendrickson

IPC: G11C16/26 ,  G11C16/04 ,  G11C11/56

CPC classification number: G11C16/26 ,  G11C7/1033 ,  G11C7/1036 ,  G11C7/1039 ,  G11C7/106 ,  G11C11/5642 ,  G11C16/0458 ,  G11C16/0483 ,  G11C2207/2272 ,  G11C2211/5642

Abstract: Methods of operating a memory device include determining whether each memory cell selected for a sense operation has any data state of a first subset of data states of a plurality of data states, wherein whether a memory cell has a data state that is a member of the first subset of data states determines a data value of a first portion of the data state of that memory cell. The methods further include initiating a transfer of the data values of the first portions of the data states of the selected memory cells and continuing the particular sense operation to sense for additional data states of the plurality of data states.

Abstract translation: 操作存储设备的方法包括确定为感测操作选择的每个存储器单元是否具有多个数据状态的数据状态的第一子集的任何数据状态，其中存储器单元是否具有作为 数据状态的第一子集确定该存储单元的数据状态的第一部分的数据值。 所述方法还包括启动所选择的存储器单元的数据状态的第一部分的数据值的传送，并且继续特定感测操作以感测多个数据状态的附加数据状态。