公开(公告)号：US09209852B2

公开(公告)日：2015-12-08

申请号：US14492891

申请日：2014-09-22

Applicant: MaxLinear, Inc.

Inventor： Kishore Seendripu ,  Raja Pullela ,  Madhukar Reddy ,  Tim Gallagher

IPC: H04B1/38 ,  H04B1/40 ,  H04L25/02 ,  H04L27/20 ,  H04L27/22 ,  H04H60/19 ,  H04B1/00 ,  H04L27/36 ,  H04L27/38

CPC classification number: H04B1/745 ,  H04B1/0067 ,  H04B1/40 ,  H04H60/19 ,  H04L25/02 ,  H04L27/20 ,  H04L27/2003 ,  H04L27/22 ,  H04L27/36 ,  H04L27/362 ,  H04L27/38

Abstract: A microwave backhaul system may comprise a monolithic integrated circuit comprising an on-chip transceiver, digital baseband processing circuitry, and auxiliary interface circuitry. The on-chip transceiver may process a microwave signal from an antenna element to generate a first pair of quadrature baseband signals and convey the first pair of phase-quadrature baseband signals to the digital baseband processing circuitry. The auxiliary interface circuitry may receive one or more auxiliary signals from a source that is external to the monolithic integrated circuit and convey the one or more auxiliary signals to the digital baseband processing circuitry. The digital baseband processing circuitry may be operable to process signals to generate one or more second pairs of phase-quadrature digital baseband signals.

Abstract translation: 微波回程系统可以包括单片集成电路，其包括片上收发器，数字基带处理电路和辅助接口电路。 片上收发器可以处理来自天线元件的微波信号以产生第一对正交基带信号，并将第一对相位正交基带信号传送到数字基带处理电路。 辅助接口电路可以从单片集成电路外部的源接收一个或多个辅助信号，并将一个或多个辅助信号传送到数字基带处理电路。 数字基带处理电路可以用于处理信号以产生一个或多个第二对相位正交数字基带信号。

公开(公告)号：US20140104499A1

公开(公告)日：2014-04-17

申请号：US13962871

申请日：2013-08-08

Applicant: MAXLINEAR, INC.

Inventor： Madhukar Reddy ,  Curtis Ling ,  Tim Gallagher

IPC: H04N5/50 ,  H04N21/438 ,  H04N21/454 ,  H04N21/426

CPC classification number: H04N21/4263 ,  H04B1/0014 ,  H04N5/455 ,  H04N5/50 ,  H04N21/4382 ,  H04N21/4383 ,  H04N21/454 ,  H04N21/6143 ,  H04N21/6193

Abstract: A wideband receiver system is provided to concurrently receive multiple RF channels including a number of desired channels that are located in non-contiguous portions of a radio frequency spectrum and to group the number of desired channels into a contiguous frequency band. The system includes a wideband receiver having a complex mixer for down-shifting the multiple RF channels and transforming them to an in-phase signal and a quadrature signal in the baseband. The system further includes a wideband analog-to-digital converter module that digitizes the in-phase and quadrature signals and a digital frontend module that transforms the digital in-phase and quadrature signals to baseband signals that contains only the number of desired RF channels that are now located in a contiguous frequency band. An up-converter module up-shifts the baseband signals to a contiguous band in an IF spectrum so that the system can directly interface with commercially available demodulators.

Abstract translation: 提供宽带接收机系统以同时接收多个RF信道，包括位于无线电频谱的非连续部分中的多个期望信道，并将期望信道的数目分组成连续的频带。 该系统包括具有复合混频器的宽带接收机，用于对多个RF信道进行下变频并将其变换成基带中的同相信号和正交信号。 该系统还包括将同相和正交信号数字化的宽带模数转换器模块和将数字同相和正交信号转换成仅包含所需RF频道数量的基带信号的数字前端模块， 现在位于连续的频带。 上变频器模块将基带信号升级到IF频谱中的连续频带，使系统可以直接与市售解调器接口。

公开(公告)号：US10693695B2

公开(公告)日：2020-06-23

申请号：US15896637

申请日：2018-02-14

Applicant: Maxlinear, Inc.

Inventor： Curtis Ling ,  Tim Gallagher ,  Elad Shaked

IPC: H04L27/26 ,  H04J11/00

Abstract: A transmitter comprises a first peak-to-average-power ratio (PAPR) suppression circuit and a second peak-to-average-power ratio (PAPR) suppression circuit. The first PAPR suppression circuit may receive a first sequence of time-domain symbols to be transmitted, alter the first sequence based on each of a plurality of symbol ordering and/or inversion descriptors to generate a corresponding plurality of second sequences of time-domain symbols, measure a PAPR corresponding to each of the second sequences, select one of the plurality of symbol ordering and/or inversion descriptors based on the measurement of PAPR, and convey the selected one of the symbol ordering and/or inversion descriptors to the second PAPR suppression circuit. The second PAPR suppression circuit may receive the first sequence of time-domain symbols to be transmitted, and alter the first sequence based on the selected one of the symbol ordering and/or inversion descriptors to generate a reordered and/or inverted symbol sequence.

公开(公告)号：US20160088344A1

公开(公告)日：2016-03-24

申请号：US14948907

申请日：2015-11-23

Applicant: MaxLinear, Inc.

Inventor： Madhukar Reddy ,  Curtis Ling ,  Tim Gallagher

IPC: H04N21/438 ,  H04B1/00 ,  H04N21/61 ,  H04N21/426 ,  H04N5/455 ,  H04N21/454

CPC classification number: H04N21/4263 ,  H04B1/0014 ,  H04N5/455 ,  H04N5/50 ,  H04N21/4382 ,  H04N21/4383 ,  H04N21/454 ,  H04N21/6143 ,  H04N21/6193

Abstract: A wideband receiver system comprises a mixer module, a wideband analog-to-digital converter (ADC) module, and digital circuitry. The mixer module is configured to downconvert a plurality of frequencies that comprises a plurality of desired television channels and a plurality of undesired television channels. The wideband ADC module is configured to digitize the swatch of frequencies comprising the plurality of desired television channels and the plurality of undesired television channels. The digital circuitry is configured to select the desired plurality of television channels from the digitized plurality of frequencies, and output the selected plurality of television channels to a demodulator as a digital datastream.

公开(公告)号：US09210363B2

公开(公告)日：2015-12-08

申请号：US14617973

申请日：2015-02-10

Applicant: MaxLinear, Inc.

Inventor： Madhukar Reddy ,  Curtis Ling ,  Tim Gallagher

IPC: H04B1/16 ,  H04N5/50 ,  H04B1/00 ,  H04N21/426 ,  H04N21/438 ,  H04N21/454 ,  H04N21/61

CPC classification number: H04N21/4263 ,  H04B1/0014 ,  H04N5/455 ,  H04N5/50 ,  H04N21/4382 ,  H04N21/4383 ,  H04N21/454 ,  H04N21/6143 ,  H04N21/6193

Abstract: A wideband receiver system comprises a wideband analog-to-digital converter (ADC) module and a digital frontend (DFE) module. The wideband ADC is configured to concurrently digitize a band of frequencies comprising a plurality of desired channels and a plurality of undesired channels. The DFE module is coupled to the digital in-phase and quadrature signals. The DFE module is configured to select the plurality of desired channels from the digitized band of frequencies, and generate an intermediate frequency (IF) signal comprising the selected plurality of desired channels and having a bandwidth that is less than a bandwidth of the band of frequencies, where the generation comprises frequency shifting of the selected plurality of desired channels. The IF signal may be a digital signal and the DFE is configured to output the IF signal via a serial or parallel interface.

Abstract translation: 宽带接收机系统包括宽带模数转换器（ADC）模块和数字前端（DFE）模块。 宽带ADC被配置为同时数字化包括多个期望信道和多个不期望信道的频带。 DFE模块耦合到数字同相和正交信号。 DFE模块被配置为从数字化的频带选择多个期望的信道，并且生成包括所选择的多个期望信道并且具有小于频带的带宽的带宽的中频（IF）信号 ，其中所述一代包括所选择的多个期望信道的频移。 IF信号可以是数字信号，并且DFE被配置为经由串行或并行接口输出IF信号。

公开(公告)号：US09210362B2

公开(公告)日：2015-12-08

申请号：US14614543

申请日：2015-02-05

Applicant: MaxLinear, Inc.

Inventor： Madhukar Reddy ,  Curtis Ling ,  Tim Gallagher

IPC: H04B1/16 ,  H04N5/50 ,  H04B1/00 ,  H04N21/426 ,  H04N21/438 ,  H04N21/454 ,  H04N21/61

CPC classification number: H04N21/4263 ,  H04B1/0014 ,  H04N5/455 ,  H04N5/50 ,  H04N21/4382 ,  H04N21/4383 ,  H04N21/454 ,  H04N21/6143 ,  H04N21/6193

Abstract: A wideband receiver system comprises a mixer module, a wideband analog-to-digital converter (ADC) module, and digital circuitry. The mixer module is configured to downconvert a plurality of frequencies that comprises a plurality of desired television channels and a plurality of undesired television channels. The wideband ADC module is configured to digitize the swatch of frequencies comprising the plurality of desired television channels and the plurality of undesired television channels. The digital circuitry is configured to select the desired plurality of television channels from the digitized plurality of frequencies, and output the selected plurality of television channels to a demodulator as a digital datastream.

Abstract translation: 宽带接收机系统包括混频器模块，宽带模数转换器（ADC）模块和数字电路。 混频器模块被配置为对包括多个所需电视频道和多个不期望的电视频道的多个频率进行下变频。 宽带ADC模块被配置为数字化包括多个所需电视频道和多个不想要的电视频道的频率的频率。 数字电路被配置为从数字化的多个频率中选择期望的多个电视频道，并且将所选择的多个电视频道作为数字数据流输出到解调器。

公开(公告)号：US20150189224A1

公开(公告)日：2015-07-02

申请号：US14586150

申请日：2014-12-30

Applicant: MaxLinear, Inc.

Inventor： Tim Gallagher ,  Glenn Delucio ,  Brijesh Sirpatil

IPC: H04N7/015 ,  H04N7/081 ,  H04N7/08

CPC classification number: H04N7/015 ,  H04N21/236 ,  H04N21/434 ,  H04N21/631 ,  H04N21/845

Abstract: Systems and methods are provided for communication ultra-high definition (UHD) video. At the transmitter-side, a single packet stream may be generated based on a plurality of UHD video streams; and the single packet stream may be split into a plurality of sub-streams, with each sub-steam comprising at least one or more packets from the single packet stream. The plurality of sub-streams may be processes concurrently via a plurality of transmit paths, to generate a corresponding plurality of signals for transmission over a particular physical medium. At the receiver-side, the plurality of signals may be concurrently received and processed, via a plurality of receive paths, and the plurality of sub-streams may be reconstructed based on processing of the plurality signals. The plurality of sub-streams may be combined to re-generate the single packet stream; and the plurality of encoded UHD video streams may then be extracted from the single packet steam.

Abstract translation: 提供了用于通信超高清（UHD）视频的系统和方法。 在发射机侧，可以基于多个UHD视频流来生成单个分组流; 并且单个分组流可以被分割成多个子流，其中每个子流包括来自单个分组流的至少一个或多个分组。 多个子流可以是经由多个发送路径同时进行的处理，以产生用于在特定物理介质上传输的对应的多个信号。 在接收机侧，可以经由多个接收路径同时接收和处理多个信号，并且可以基于多个信号的处理重建多个子流。 可以组合多个子流以重新生成单个分组流; 然后可以从单个分组流中提取多个编码的UHD视频流。

公开(公告)号：US20180063570A1

公开(公告)日：2018-03-01

申请号：US15792318

申请日：2017-10-24

Applicant: Maxlinear, Inc.

Inventor： Madhukar Reddy ,  Curtis Ling ,  Tim Gallagher

IPC: H04N21/426 ,  H04N21/438 ,  H04N21/61 ,  H04B1/00 ,  H04N5/455 ,  H04N5/50 ,  H04N21/454

CPC classification number: H04N21/4263 ,  H04B1/0014 ,  H04N5/455 ,  H04N5/50 ,  H04N21/4382 ,  H04N21/4383 ,  H04N21/454 ,  H04N21/6143 ,  H04N21/6193

Abstract: A wideband receiver system comprises a wideband analog-to-digital converter (ADC) module and a digital frontend (DFE) module. The wideband ADC is configured to concurrently digitize a band of frequencies comprising a plurality of desired channels and a plurality of undesired channels. The DFE module is coupled to the digital in-phase and quadrature signals. The DFE module is configured to select the plurality of desired channels from the digitized band of frequencies, and generate an intermediate frequency (IF) signal comprising the selected plurality of desired channels and having a bandwidth that is less than a bandwidth of the band of frequencies, where the generation comprises frequency shifting of the selected plurality of desired channels. The IF signal may be a digital signal and the DFE is configured to output the IF signal via a serial or parallel interface.

公开(公告)号：US09819992B2

公开(公告)日：2017-11-14

申请号：US14948881

申请日：2015-11-23

Applicant: MaxLinear, Inc.

Inventor： Madhukar Reddy ,  Curtis Ling ,  Tim Gallagher

IPC: H04B1/16 ,  H04N21/40 ,  H04H40/90 ,  H04N21/426 ,  H04B1/00 ,  H04N5/50 ,  H04N21/438 ,  H04N21/454 ,  H04N21/61 ,  H04N5/455

CPC classification number: H04N21/4263 ,  H04B1/0014 ,  H04N5/455 ,  H04N5/50 ,  H04N21/4382 ,  H04N21/4383 ,  H04N21/454 ,  H04N21/6143 ,  H04N21/6193

Abstract: A wideband receiver system comprises a wideband analog-to-digital converter (ADC) module and a digital frontend (DFE) module. The wideband ADC is configured to concurrently digitize a band of frequencies comprising a plurality of desired channels and a plurality of undesired channels. The DFE module is coupled to the digital in-phase and quadrature signals. The DFE module is configured to select the plurality of desired channels from the digitized band of frequencies, and generate an intermediate frequency (IF) signal comprising the selected plurality of desired channels and having a bandwidth that is less than a bandwidth of the band of frequencies, where the generation comprises frequency shifting of the selected plurality of desired channels. The IF signal may be a digital signal and the DFE is configured to output the IF signal via a serial or parallel interface.

公开(公告)号：US20160088337A1

公开(公告)日：2016-03-24

申请号：US14948881

申请日：2015-11-23

Applicant: MaxLinear, Inc.

Inventor： Madhukar Reddy ,  Curtis Ling ,  Tim Gallagher

IPC: H04N21/426 ,  H04N21/438 ,  H04N21/454 ,  H04N21/61

CPC classification number: H04N21/4263 ,  H04B1/0014 ,  H04N5/455 ,  H04N5/50 ,  H04N21/4382 ,  H04N21/4383 ,  H04N21/454 ,  H04N21/6143 ,  H04N21/6193

Abstract: A wideband receiver system comprises a wideband analog-to-digital converter (ADC) module and a digital frontend (DFE) module. The wideband ADC is configured to concurrently digitize a band of frequencies comprising a plurality of desired channels and a plurality of undesired channels. The DFE module is coupled to the digital in-phase and quadrature signals. The DFE module is configured to select the plurality of desired channels from the digitized band of frequencies, and generate an intermediate frequency (IF) signal comprising the selected plurality of desired channels and having a bandwidth that is less than a bandwidth of the band of frequencies, where the generation comprises frequency shifting of the selected plurality of desired channels. The IF signal may be a digital signal and the DFE is configured to output the IF signal via a serial or parallel interface.

Abstract translation: 宽带接收机系统包括宽带模数转换器（ADC）模块和数字前端（DFE）模块。 宽带ADC被配置为同时数字化包括多个期望信道和多个不期望信道的频带。 DFE模块耦合到数字同相和正交信号。 DFE模块被配置为从数字化的频带选择多个期望的信道，并且生成包括所选择的多个期望信道并且具有小于频带的带宽的带宽的中频（IF）信号 ，其中所述一代包括所选择的多个期望信道的频移。 IF信号可以是数字信号，并且DFE被配置为经由串行或并行接口输出IF信号。