公开(公告)号：US11763889B2

公开(公告)日：2023-09-19

申请号：US17706087

申请日：2022-03-28

Applicant: Micron Technology, Inc.

Inventor： Benben Li ,  Akira Goda ,  Ramey M. Abdelrahaman ,  Ian C. Laboriante ,  Krishna K. Parat

IPC: G11C16/04 ,  G11C11/408 ,  G11C8/08 ,  H10B41/27 ,  H10B41/35 ,  H10B41/60 ,  H10B43/27 ,  H10B43/35 ,  H10B51/20 ,  H10B63/00 ,  H10N70/00

CPC classification number: G11C16/0475 ,  G11C8/08 ,  G11C11/4087 ,  H10B41/27 ,  H10B41/35 ,  H10B41/60 ,  H10B43/27 ,  H10B43/35 ,  H10B51/20 ,  H10B63/84 ,  H10N70/883 ,  G11C16/0483

Abstract: Some embodiments include apparatuses and methods of forming such apparatuses. One of the apparatus includes first memory cells located in different levels in a first portion of the apparatus, second memory cells located in different levels in a second portion of the apparatus, a switch located in a third portion of the apparatus between the first and second portions, first and second control gates to access the first and second memory cells, an additional control gate located between the first and second control gates to control the switch, a first conductive structure having a thickness and extending perpendicular to the levels in the first portion of the apparatus, a first dielectric structure between the first conductive structure and charge-storage portions of the first memory cells, a second dielectric structure having a second thickness between the second conductive structure and a sidewall of the additional control gate, the second thickness being greater than the first thickness.

公开(公告)号：US10748921B2

公开(公告)日：2020-08-18

申请号：US16171160

申请日：2018-10-25

Applicant: Micron Technology, Inc.

Inventor： Liu Liu ,  David Daycock ,  Rithu K. Bhonsle ,  Giovanni Mazzone ,  Narula Bilik ,  Jordan D. Greenlee ,  Minsoo Lee ,  Benben Li

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L21/32 ,  H01L27/1157 ,  H01L21/311 ,  H01L27/11556

Abstract: Some embodiments include a method of forming stacked memory decks. A first deck has first memory cells arranged in first tiers disposed one atop another, and has a first channel-material pillar extending through the first tiers. An inter-deck structure is over the first deck. The inter-deck structure includes an insulative expanse, and a region extending through the insulative expanse and directly over the first channel-material pillar. The region includes an etch-stop structure. A second deck is formed over the inter-deck structure. The second deck has second memory cells arranged in second tiers disposed one atop another. An opening is formed to extend through the second tiers and to the etch-stop structure. The opening is subsequently extended through the etch-stop structure. A second channel-material pillar is formed within the opening and is coupled to the first channel-material pillar. Some embodiments include integrated assemblies.