公开(公告)号：US20240196606A1

公开(公告)日：2024-06-13

申请号：US18513430

申请日：2023-11-17

Applicant: Micron Technology, Inc.

Inventor： Lifang Xu ,  Harsh Narendrakumar Jain ,  Indra V. Chary ,  Richard J. Hill

IPC: H10B41/35 ,  G11C5/02 ,  G11C16/04 ,  H10B41/10 ,  H10B41/20 ,  H10B43/10 ,  H10B43/20 ,  H10B43/35

CPC classification number: H10B41/35 ,  G11C5/025 ,  G11C16/0483 ,  H10B41/10 ,  H10B41/20 ,  H10B43/10 ,  H10B43/20 ,  H10B43/35

Abstract: A microelectronic device includes a stack structure comprising blocks, additional dielectric slot structures, and a further dielectric slot structure. The stack structure includes alternating tiers of conductive and insulative structures. A block comprises a stadium structure and crest regions. The stadium structure includes staircase structures having steps comprising edges of the tiers. The additional dielectric slot structures individually extend in the first direction across a first of the crest regions and at least partially into the stadium structure. The additional dielectric slot structures are separated from one another in a second direction orthogonal to the first direction and individually vertically extend through the tiers. The further dielectric slot structure extends in the second direction across a second of the crest regions. The further dielectric slot structure intersects at least one of the additional dielectric slot structures and vertically extend through the tiers.

公开(公告)号：US11856763B2

公开(公告)日：2023-12-26

申请号：US17205954

申请日：2021-03-18

Applicant: Micron Technology, Inc.

Inventor： Lifang Xu ,  Sidhartha Gupta ,  Kar Wui Thong ,  Harsh Narendrakumar Jain

IPC: H10B41/27 ,  H01L29/78 ,  H01L29/66 ,  G11C5/06 ,  H10B43/27

CPC classification number: H10B41/27 ,  G11C5/06 ,  H01L29/66666 ,  H01L29/7827 ,  H10B43/27

Abstract: A method of forming a microelectronic device including a first stack structure comprising alternating levels of insulative structures and other insulative structures, forming strings of memory cells through the first stack structure, forming a second stack structure over the first stack structure, based at least partially on observed amount of pillar bending within the first stack structure, forming a first tailored reticle specific to the observed amount of pillar bending, utilizing the first tailored reticle to form openings extending through the second stack structure and over some of the strings of memory cells, wherein centers of the openings over the strings of memory cells are at least substantially aligned with the centers of uppermost surfaces of the strings of memory cells in a direction of the observed pillar bending, and forming upper pillars extending through the second stack structure and over some of the strings of memory cells.

公开(公告)号：US20230326793A1

公开(公告)日：2023-10-12

申请号：US18200852

申请日：2023-05-23

Applicant: Micron Technology, Inc.

Inventor： Kar Wui Thong ,  Harsh Narendrakumar Jain ,  John Hopkins

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H01L23/535 ,  H10B41/27 ,  H10B43/27

CPC classification number: H01L21/76897 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/535 ,  H10B41/27 ,  H10B43/27

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes levels of conductive materials interleaved with levels of dielectric materials; memory cell strings including respective pillars extending through the levels of conductive materials and the levels of dielectric materials; a dielectric structure formed in a slit, the slit extending through the levels of conductive materials and the levels of dielectric materials, the dielectric structure separating the levels of conductive materials and the levels of dielectric materials into a first portion and a second portion; first conductive structures located over and coupled to respective pillars of the first memory cell strings; second conductive structures located over and coupled to respective pillars of the second memory cell strings; and a conductive line contacting the dielectric structure, a conductive structure of the first conductive structures, and a conductive structure of the second conductive structures.

公开(公告)号：US20230317601A1

公开(公告)日：2023-10-05

申请号：US17709020

申请日：2022-03-30

Applicant: Micron Technology, Inc.

Inventor： Harsh Narendrakumar Jain ,  Scott L. Light ,  Shruthi Kumara Vadivel ,  Shuangqiang Luo

IPC: H01L23/528 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L21/76895

Abstract: Microelectronic devices include a tiered stack comprising a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. A stadium within the tiered stack includes a staircase with steps at ends of some of the tiers. The steps each have a tread provided by an upper surface portion of one of the conductive structures. Conductive contact structures extend to one of the steps and include a first conductive contact structure terminating at the tread of the step and a second conductive contact structure extending through the tread of the step. Related fabrication methods and electronic systems are also disclosed.

公开(公告)号：US11700727B2

公开(公告)日：2023-07-11

申请号：US17111275

申请日：2020-12-03

Applicant: Micron Technology, Inc.

Inventor： Shruthi Kumara Vadivel ,  Yi Hu ,  Harsh Narendrakumar Jain

IPC: H10B41/27 ,  G11C5/06 ,  G11C5/02 ,  H10B43/27 ,  H10B43/10 ,  H10B43/50 ,  H10B41/35 ,  H10B41/50 ,  H10B43/35

CPC classification number: H10B41/27 ,  G11C5/025 ,  G11C5/06 ,  H10B41/35 ,  H10B41/50 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/50

Abstract: A microelectronic device comprises a stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers. The stack structure comprises a first block structure comprising stair step structures spaced from each other by crest regions, the stair step structures each comprising steps defined at horizontal edges of the tiers of the conductive structures and the insulative structures, and a second block structure horizontally neighboring the first block structure and comprising additional stair step structures spaced from one another by additional crest regions, the additional stair step structures horizontally offset from the stair step structures of the first block structure, and a slot structure extending though the stack structure and interposed between the first block structure and the second block structure. Related microelectronic devices, electronic systems, and methods are also described.

公开(公告)号：US11417681B2

公开(公告)日：2022-08-16

申请号：US17215308

申请日：2021-03-29

Applicant: Micron Technology, Inc.

Inventor： Yi Hu ,  Merri L. Carlson ,  Anilkumar Chandolu ,  Indra V. Chary ,  David Daycock ,  Harsh Narendrakumar Jain ,  Matthew J. King ,  Jian Li ,  Brett D. Lowe ,  Prakash Rau Mokhna Rau ,  Lifang Xu

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11565 ,  H01L21/28 ,  H01L21/768 ,  H01L27/115 ,  H01L21/311 ,  H01L21/02 ,  H01L27/11526 ,  H01L27/11519 ,  H01L27/11573 ,  H01L21/3213

Abstract: A method used in forming a memory array comprising strings of memory cells and operative through-array-vias (TAVs) comprises forming a stack comprising vertically-alternating insulative tiers and conductive tiers. The stack comprises a TAV region and an operative memory-cell-string region. The TAV region comprises spaced operative TAV areas. Operative channel-material strings are formed in the stack in the operative memory-cell-string region and dummy channel-material strings are formed in the stack in the TAV region laterally outside of and not within the operative TAV areas. Operative TAVs are formed in individual of the spaced operative TAV areas in the TAV region. Other methods and structure independent of method are disclosed.

公开(公告)号：US20220181342A1

公开(公告)日：2022-06-09

申请号：US17111275

申请日：2020-12-03

Applicant: Micron Technology, Inc.

Inventor： Shruthi Kumara Vadivel ,  Yi Hu ,  Harsh Narendrakumar Jain

IPC: H01L27/11556 ,  H01L27/11582 ,  G11C5/02 ,  G11C5/06

Abstract: A microelectronic device comprises a stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers. The stack structure comprises a first block structure comprising stair step structures spaced from each other by crest regions, the stair step structures each comprising steps defined at horizontal edges of the tiers of the conductive structures and the insulative structures, and a second block structure horizontally neighboring the first block structure and comprising additional stair step structures spaced from one another by additional crest regions, the additional stair step structures horizontally offset from the stair step structures of the first block structure, and a slot structure extending though the stack structure and interposed between the first block structure and the second block structure. Related microelectronic devices, electronic systems, and methods are also described.

公开(公告)号：US20210351127A1

公开(公告)日：2021-11-11

申请号：US17385299

申请日：2021-07-26

Applicant: Micron Technology, Inc.

Inventor： Yi Hu ,  Harsh Narendrakumar Jain ,  Matthew J. King

IPC: H01L23/522 ,  H01L23/528 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11524 ,  H01L21/311 ,  H01L21/762

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The intervening material comprises longitudinally-alternating first and second regions that individually have a vertically-elongated seam therein. The vertically-elongated seam in the first regions has a higher top than in the second regions. The seam tops in the second regions are elevationally-coincident with or below a bottom of an uppermost of the conductive tiers. Methods are disclosed.

公开(公告)号：US20210043644A1

公开(公告)日：2021-02-11

申请号：US16532019

申请日：2019-08-05

Applicant: Micron Technology, Inc.

Inventor： Yi Hu ,  Merri L. Carlson ,  Anilkumar Chandolu ,  Indra V. Chary ,  David Daycock ,  Harsh Narendrakumar Jain ,  Matthew J. King ,  Jian Li ,  Brett D. Lowe ,  Prakash Rau Mokhna Rau ,  Lifang Xu

IPC: H01L27/11582 ,  H01L21/311 ,  H01L21/02 ,  H01L27/11526 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573 ,  H01L21/3213

Abstract: A method used in forming a memory array comprising strings of memory cells and operative through-array-vias (TAVs) comprises forming a stack comprising vertically-alternating insulative tiers and conductive tiers. The stack comprises a TAV region and an operative memory-cell-string region. The TAV region comprises spaced operative TAV areas. Operative channel-material strings are formed in the stack in the operative memory-cell-string region and dummy channel-material strings are formed in the stack in the TAV region laterally outside of and not within the operative TAV areas. Operative TAVs are formed in individual of the spaced operative TAV areas in the TAV region. Other methods and structure independent of method are disclosed.

公开(公告)号：US20250167130A1

公开(公告)日：2025-05-22

申请号：US19030527

申请日：2025-01-17

Applicant: Micron Technology, Inc.

Inventor： Rohit Kothari ,  Harsh Narendrakumar Jain ,  John D. Hopkins ,  Xiaosong Zhang

IPC: H01L23/544

Abstract: An electronic device comprising a multideck structure including a base stack of materials and one or more stacks of materials on the base stack of materials, at least one high aspect ratio feature in an array region in the base stack of materials and in the one or more stacks of materials, and overlay marks including an optical contrast material in or on only an upper portion of the base stack of materials in an overlay mark region of the electronic device is disclosed. The overlay mark region is laterally adjacent to the array region and the overlay marks are adjacent to at least one additional high aspect ratio feature in the base stack of materials. Additional electronic devices and memory devices are disclosed.