公开(公告)号：US09842649B2

公开(公告)日：2017-12-12

申请号：US15185767

申请日：2016-06-17

Applicant: Micron Technology, Inc.

Inventor： Seshadri K. Kolluri ,  Rajesh N. Gupta

IPC: G11C11/00 ,  G11C13/00 ,  G11C11/56

CPC classification number: G11C13/0097 ,  G11C11/56 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2013/0092 ,  G11C2213/79

Abstract: Apparatus and methods are disclosed, including a method that performs a first operation on a first resistance variable element using a common source voltage, a first data line voltage and a first control gate voltage, and then performs a second operation on a second resistance variable element using the common source voltage, a second data line voltage and a second control gate voltage. Additional apparatus and methods are described.

公开(公告)号：US09761590B1

公开(公告)日：2017-09-12

申请号：US15162028

申请日：2016-05-23

Applicant: Micron Technology, Inc.

Inventor： Srinivas Pulugurtha ,  Sourabh Dhir ,  Rajesh N. Gupta ,  Sanh D. Tang ,  Si-Woo Lee ,  Haitao Liu

IPC: H01L23/52 ,  H01L27/108 ,  H01L29/06 ,  H01L27/088 ,  H01L23/528 ,  G11C11/4078

CPC classification number: H01L27/10826 ,  G11C7/02 ,  G11C11/404 ,  G11C11/4078 ,  H01L23/528 ,  H01L27/0886 ,  H01L29/0649

Abstract: A method for memory device fabrication includes forming a plurality of continuous fins on a substrate. An insulator material is formed around the fins. The continuous fins are etched into segmented fins to form exposed areas between the segmented fins. An insulator material is formed in the exposed areas wherein the insulator material in the exposed areas is formed higher than the insulator material around the fins. A metal is formed over the fins and the insulator material. The metal formed over the exposed areas is formed to a shallower depth than over the fins.

公开(公告)号：US20150311254A1

公开(公告)日：2015-10-29

申请号：US14740738

申请日：2015-06-16

Applicant: Micron Technology, Inc.

Inventor： Rajesh N. Gupta ,  Farid Nemati

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2454 ,  G11C11/161 ,  G11C11/1659 ,  H01L27/228 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16 ,  H01L45/1608

Abstract: Arrays of memory cells having a common gate terminal and methods of operating and forming the same are described herein. As an example, an array of memory cells may include a group of memory cells each having a resistive storage element coupled to a select device. Each select device includes a first terminal, a second terminal, and a gate terminal, where the gate terminal is common to each memory cell of the group.

Abstract translation: 这里描述了具有公共栅极端子的存储单元阵列及其操作和形成方法。 作为示例，存储器单元阵列可以包括一组存储器单元，每个存储单元具有耦合到选择器件的电阻存储元件。 每个选择装置包括第一端子，第二端子和栅极端子，其中栅极端子对于该组的每个存储器单元是公用的。

公开(公告)号：US20140247674A1

公开(公告)日：2014-09-04

申请号：US13782792

申请日：2013-03-01

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kamal M. Karda ,  Rajesh N. Gupta ,  Srinivas Pulugurtha ,  Chandra V. Mouli ,  Wolfgang Mueller

IPC: H01L29/78 ,  G11C11/40

CPC classification number: H01L29/7827 ,  G11C11/40 ,  H01L27/0207 ,  H01L27/1052 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10885 ,  H01L27/10891 ,  H01L29/66666

Abstract: Methods, apparatuses, and systems for providing a body connection to a vertical access device. The vertical access device may include a digit line extending along a substrate to a digit line contact pillar, a body connection line extending along the substrate to a body connection line contact pillar, a body region disposed on the body connection line, an electrode disposed on the body region, and a word line extending to form a gate to the body region. A method for operation includes applying a first voltage to the body connection line, and applying a second voltage to the word line to cause a conductive channel to form through the body region. A memory cell array may include a plurality of vertical access devices.

Abstract translation: 用于向垂直存取装置提供身体连接的方法，装置和系统。 垂直进入装置可以包括沿着基板延伸到数字线接触柱的数字线，沿着基板延伸到主体连接线接触柱的主体连接线，设置在主体连接线上的主体区域，设置在主体连接线上的电极 身体区域和延伸以形成到身体区域的门的字线。 一种操作方法包括：将第一电压施加到身体连接线，以及向该字线施加第二电压，以使导电通道通过身体区域形成。 存储单元阵列可以包括多个垂直存取装置。

公开(公告)号：US11442631B2

公开(公告)日：2022-09-13

申请号：US16727196

申请日：2019-12-26

Applicant: Micron Technology, Inc.

Inventor： Rajesh N. Gupta

IPC: G06F3/06 ,  G06F12/1009

Abstract: As described herein, an apparatus may include a memory that includes a first portion, a second portion, and a third portion. The apparatus may also include a memory controller that includes a first logical-to-physical table stored in a buffer memory. The memory controller may determine that the first portion is accessed sequential to the second portion and may adjust the first logical-to-physical table to cause a memory transaction performed by the memory controller to access the third portion as opposed to the first portion.

公开(公告)号：US11302703B2

公开(公告)日：2022-04-12

申请号：US16803948

申请日：2020-02-27

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Chandra Mouli ,  Srinivas Pulugurtha ,  Rajesh N. Gupta

IPC: H01L27/112 ,  H01L27/108 ,  H01L49/02 ,  G11C11/4074 ,  H01L29/08 ,  H01L27/11556 ,  H01L21/8234 ,  H01L21/84 ,  H01L21/8238 ,  H01L27/11582 ,  G11C11/408 ,  H01L27/07 ,  H01L27/11553 ,  H01L29/92 ,  G11C5/14 ,  G11C5/06

Abstract: Some embodiments include a memory cell with two transistors and one capacitor. The transistors are a first transistor and a second transistor. The capacitor has a first node coupled with a source/drain region of the first transistor, and has a second node coupled with a source/drain region of the second transistor. The memory cell has a first body region adjacent the source/drain region of the first transistor, and has a second body region adjacent the source/drain region of the second transistor. A first body connection line couples the first body region of the memory cell to a first reference voltage. A second body connection line couples the second body region of the memory cell to a second reference voltage. The first and second reference voltages may be the same as one another, or may be different from one another.

公开(公告)号：US20210200447A1

公开(公告)日：2021-07-01

申请号：US16727196

申请日：2019-12-26

Applicant: Micron Technology, Inc.

Inventor： Rajesh N. Gupta

IPC: G06F3/06 ,  G06F12/1009

Abstract: As described herein, an apparatus may include a memory that includes a first portion, a second portion, and a third portion. The apparatus may also include a memory controller that includes a first logical-to-physical table stored in a buffer memory. The memory controller may determine that the first portion is accessed sequential to the second portion and may adjust the first logical-to-physical table to cause a memory transaction performed by the memory controller to access the third portion as opposed to the first portion.

公开(公告)号：US10886273B2

公开(公告)日：2021-01-05

申请号：US16436689

申请日：2019-06-10

Applicant: Micron Technology, Inc.

Inventor： Rajesh N. Gupta ,  Farid Nemati ,  Scott T. Robins

IPC: H01L21/8249 ,  H01L27/102 ,  H01L29/735 ,  H01L29/73 ,  H01L21/02 ,  H01L21/8229 ,  H01L29/16 ,  H01L29/732 ,  H01L29/739 ,  H01L27/108 ,  H01L29/78

Abstract: Some embodiments include gated bipolar junction transistors. The transistors may include a base region between a collector region and an emitter region; with a B-C junction being at an interface of the base region and the collector region, and with a B-E junction being at an interface of the base region and the emitter region. The transistors may include material having a bandgap of at least 1.2 eV within one or more of the base, emitter and collector regions. The gated transistors may include a gate along the base region and spaced from the base region by dielectric material, with the gate not overlapping either the B-C junction or the B-E junction. Some embodiments include memory arrays containing gated bipolar junction transistors. Some embodiments include methods of forming gated bipolar junction transistors.

公开(公告)号：US10381357B2

公开(公告)日：2019-08-13

申请号：US16043653

申请日：2018-07-24

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Chandra Mouli ,  Srinivas Pulugurtha ,  Rajesh N. Gupta

IPC: H01L27/112 ,  H01L27/108 ,  H01L49/02 ,  G11C11/4074 ,  H01L29/08 ,  H01L27/11556 ,  H01L21/8234 ,  H01L21/84 ,  H01L21/8238 ,  H01L27/11582 ,  G11C11/408 ,  G11C5/14 ,  G11C5/06

Abstract: Some embodiments include a memory cell with two transistors and one capacitor. The transistors are a first transistor and a second transistor. The capacitor has a first node coupled with a source/drain region of the first transistor, and has a second node coupled with a source/drain region of the second transistor. The memory cell has a first body region adjacent the source/drain region of the first transistor, and has a second body region adjacent the source/drain region of the second transistor. A first body connection line couples the first body region of the memory cell to a first reference voltage. A second body connection line couples the second body region of the memory cell to a second reference voltage. The first and second reference voltages may be the same as one another, or may be different from one another.

公开(公告)号：US20180166138A1

公开(公告)日：2018-06-14

申请号：US15837896

申请日：2017-12-11

Applicant: Micron Technology, Inc.

Inventor： Seshadri K. Kolluri ,  Rajesh N. Gupta

IPC: G11C13/00 ,  G11C11/56

CPC classification number: G11C13/0097 ,  G11C11/56 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2013/0092 ,  G11C2213/79

Abstract: Apparatus and methods are disclosed, including a method that performs a first operation on a first resistance variable element using a common source voltage, a first data line voltage and a first control gate voltage, and then performs a second operation on a second resistance variable element using the common source voltage, a second data line voltage and a second control gate voltage. Additional apparatus and methods are described.