公开(公告)号：US11688333B1

公开(公告)日：2023-06-27

申请号：US17646660

申请日：2021-12-30

Applicant: Microsoft Technology Licensing, LLC

Inventor： Charles Walter Boecker ,  Niranjan Achugundla Puttaswamy ,  Barry Thompson ,  Sheethal Somesh Nayak ,  Jeffrey Neil Margolis ,  Chuan Pu

IPC: G09G3/32 ,  G09G3/20

CPC classification number: G09G3/32 ,  G09G3/2022 ,  G09G3/2085 ,  G09G2300/0857 ,  G09G2320/0233

Abstract: A display device includes a display substrate and a backplane substrate. The display substrate includes an array of micro-LEDs forming individual pixels. The backplane substrate includes a plurality of pixel logic hardware modules. Each pixel logic hardware module includes a local memory element configured to store a multi-bit pixel intensity value of a corresponding micro-LED for an image frame. The backplane substrate is bonded to a backside of the display substrate such that the pixel logic hardware modules are physically aligned behind the array of micro-LEDs and each pixel logic hardware module is electrically connected to a micro-LED of the corresponding pixel.

公开(公告)号：US10306172B2

公开(公告)日：2019-05-28

申请号：US15870722

申请日：2018-01-12

Applicant: Microsoft Technology Licensing, LLC

Inventor： Barry Thompson ,  Lawrence Albert Prather

IPC: H04N5/378 ,  H04N5/374 ,  G01S7/486 ,  H04N5/3745 ,  H04N5/357 ,  G01S17/10

Abstract: A time-of-flight image sensor including a readout circuit is provided. The readout circuit may include a pixel array including multiple pixels. The pixel array may be configured to produce a pixel signal for each of one or more pixels over a series of timesteps. The pixel signal may include an illuminated value and a reset value. The readout circuit may further include a plurality of gain selection comparators configured to receive the pixel signal and select an amplifier gain value. The readout circuit may further include analog correlated double sampling circuitry. The readout circuit may further include a programmable gain amplifier configured to generate an amplified pixel signal from the pixel signal, which may be amplified at the selected amplifier gain value. The readout circuit may further include a plurality of analog-to-digital converters. Each of the analog-to-digital converters may have a common ramp generated by a global ramp generator.

公开(公告)号：US10020813B1

公开(公告)日：2018-07-10

申请号：US15666391

申请日：2017-08-01

Applicant: Microsoft Technology Licensing, LLC

Inventor： Richard McCauley ,  Barry Thompson ,  Stefan Wurster

IPC: H03L7/06 ,  H03L7/085 ,  G01S7/481

Abstract: A clocking system disclosed herein includes a delay locked loop (DLL) circuit with a plurality of delay elements, where the DLL circuit is configured to receive a clock input signal and generate a plurality of clock output signals. The clocking system also includes a feed-forward system configured to increase the speed of the clock signal transmission through the delay elements and to enforce symmetric zero crossings of the clock signal at each of the plurality of delay elements.