公开(公告)号：US20060226916A1

公开(公告)日：2006-10-12

申请号：US11103743

申请日：2005-04-11

Applicant: Octavian Florescu ,  Amr Fahim ,  Chiewcharn Narathong

Inventor： Octavian Florescu ,  Amr Fahim ,  Chiewcharn Narathong

IPC: H03L7/00

CPC classification number: H03L7/199 ,  H03L7/0898 ,  H03L7/10

Abstract: A PLL includes a charge pump, a loop filter, a VCO, and a calibration unit. The calibration unit performs coarse tuning to select one or multiple frequency ranges, performs fine tuning to determine an initial control voltage that puts the VCO near a desired operating frequency, measures the VCO gain at different control voltages, and derives VCO gain compensation values for the different control voltages. The calibration unit also pre-charges the loop filter to the initial control voltage to shorten acquisition time, enables the loop filter to drive the VCO to lock to the desired operating frequency, and performs VCO gain compensation during normal operation. For VCO gain compensation, the calibration unit measures the control voltage, obtains the VCO gain compensation value for the measured control voltage, and adjusts the gain of at least one circuit block (e.g., the charge pump) to account for variation in the VCO gain.

Abstract translation: PLL包括电荷泵，环路滤波器，VCO和校准单元。 校准单元执行粗调以选择一个或多个频率范围，执行微调以确定将VCO置于所需工作频率附近的初始控制电压，测量不同控制电压下的VCO增益，并导出VCO增益补偿值 不同的控制电压。 校准单元还将环路滤波器预充电到初始控制电压以缩短采集时间，使环路滤波器能够驱动VCO锁定到所需的工作频率，并在正常操作期间执行VCO增益补偿。 对于VCO增益补偿，校准单元测量控制电压，获得测量的控制电压的VCO增益补偿值，并调整至少一个电路块（例如，电荷泵）的增益，以考虑VCO增益的变化 。

公开(公告)号：US06911856B2

公开(公告)日：2005-06-28

申请号：US10632651

申请日：2003-07-31

Applicant: Octavian Florescu

Inventor： Octavian Florescu

IPC: G06F1/04 ,  G06F1/10 ,  H03K3/037 ,  H03K5/135 ,  H03K3/00

CPC classification number: G06F1/04 ,  G06F1/10 ,  H03K3/0372 ,  H03K3/0375 ,  H03K5/135

Abstract: Techniques for compensating for propagation delay differences between signals distributed within a logic circuit. A delay matching circuit mimics the internal clock-to-Q delay produced by a flop. The delay matching circuit is placed in the propagation path of an original signal, such as a clock signal, to be redistributed. In general, the delay matching circuit may include a propagation gate multiplexer have a particular configuration. The delay matching circuit imposes a delay substantially equal to the clock-to-Q delay experienced by divided versions of the original signal. In this manner, the delay matching circuit ensures that the rising and falling edges of the original signal and the divided signal are in substantial alignment, enabling synchronous operation. Hence, the delay matching circuit is capable of synchronizing the redistributed and divided signals.