公开(公告)号：US10944165B2

公开(公告)日：2021-03-09

申请号：US16554644

申请日：2019-08-29

Applicant: Powertech Technology Inc.

Inventor： Yun-Hsin Yeh ,  Hung-Hsin Hsu

IPC: H01Q1/38 ,  H01L21/56 ,  H01L23/31 ,  H01L23/66 ,  H01Q1/40

Abstract: An integrated antenna package structure including a circuit board, a chip, an encapsulant and an antenna is provided. The chip is disposed on and electrically connected to the circuit board. The encapsulant encapsulates the chip. The encapsulant has a first surface and a second surface, wherein the normal vector of the first surface is different from the normal vector of the second surface. The antenna is disposed on the first surface and the second surface of the encapsulant. A manufacturing method of an integrated antenna package structure is also provided.

公开(公告)号：US20210035936A1

公开(公告)日：2021-02-04

申请号：US16529796

申请日：2019-08-02

Applicant: Powertech Technology Inc.

Inventor： Nan-Chun Lin ,  Hung-Hsin Hsu ,  Shang-Yu Chang Chien

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56

Abstract: A package structure and a method of manufacturing the same are provided. The package structure includes a substrate, a redistribution layer (RDL) structure, a first die, an encapsulant and a plurality of conductive terminals. The RDL structure is disposed on and electrically connected to the substrate. A width of the RDL structure is less than a width of the substrate. The first die is disposed on the substrate and the RDL structure. The first connectors of the first die are electrically connected to the RDL structure. The second connectors of the first die are electrically connected to the substrate. A first pitch of two adjacent first connectors is less than a second pitch of two adjacent second connectors. The encapsulant is on the substrate to encapsulate the RDL structure and the first die. The conductive terminals are electrically connected to the first die through the substrate and the RDL structure.

公开(公告)号：US20200328167A1

公开(公告)日：2020-10-15

申请号：US16698869

申请日：2019-11-27

Applicant: Powertech Technology Inc.

Inventor： Shang-Yu Chang Chien ,  Hung-Hsin Hsu ,  Nan-Chun Lin

IPC: H01L23/66 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01Q1/22

Abstract: An integrated antenna package structure including a chip package and an antenna device is provided. The antenna device is disposed on the chip package. The chip package includes a chip, an encapsulant, a circuit layer, and a conductive connector. The encapsulant at least directly covers the back side of the chip. The circuit layer is disposed on the encapsulant and electrically connected to the chip. The conductive connector penetrates the encapsulant and is electrically connected to the circuit layer. The antenna device includes a dielectric body, a coupling layer, and an antenna layer. The dielectric body has a first dielectric surface and a second dielectric surface opposite to the first dielectric surface. The coupling layer is disposed on the second dielectric surface of the dielectric body. The antenna layer is disposed on the first dielectric surface of the dielectric body. The antenna layer is electrically connected to the conductive connector. A manufacturing method of an integrated antenna package structure is also provided.

公开(公告)号：US20200328144A1

公开(公告)日：2020-10-15

申请号：US16382229

申请日：2019-04-12

Applicant: Powertech Technology Inc.

Inventor： Wen-Jeng Fan ,  Shang-Yu Chang Chien ,  Nan-Chun Lin ,  Hung-Hsin Hsu

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/66 ,  H01L21/56 ,  H01L21/48

Abstract: A semiconductor package including a semiconductor chip, a conductive element disposed aside the semiconductor chip, a conductive via disposed on and electrically connected to the conductive element, an insulating encapsulation, and a first circuit structure disposed on the semiconductor chip and the conductive via is provided. A height of the conductive element is less than a height of the semiconductor chip. The insulating encapsulation encapsulates the semiconductor chip, the conductive element, and the conductive via. The conductive via is located between the first circuit structure and the conductive element, and the semiconductor chip is electrically coupled to the conductive via through the first circuit structure.

公开(公告)号：US20200091103A1

公开(公告)日：2020-03-19

申请号：US16136197

申请日：2018-09-19

Applicant: Powertech Technology Inc.

Inventor： Shang-Yu Chang Chien ,  Hung-Hsin Hsu ,  Nan-Chun Lin

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31

Abstract: A package structure including a semiconductor die, an insulating encapsulant, a dielectric layer, and a redistribution layer is provided. The semiconductor die has an active surface, a back surface opposite to the active surface, and a plurality of conductive bumps disposed on the active surface. The insulating encapsulant is encapsulating the semiconductor die. The redistribution layer is disposed on the he insulating encapsulant and electrically connected to the plurality of conductive bumps. The dielectric layer is disposed between the insulating encapsulant and the redistribution layer, wherein the dielectric layer encapsulates at least a portion of each of the plurality of conductive bumps.

公开(公告)号：US20190319000A1

公开(公告)日：2019-10-17

申请号：US15952261

申请日：2018-04-13

Applicant: Powertech Technology Inc.

Inventor： Nan-Chun Lin ,  Hung-Hsin Hsu

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31

Abstract: A package structure includes a die, an encapsulant, a dam structure, and a redistribution structure. The die has an active surface and a rear surface opposite to the active surface. The encapsulant encapsulates sidewalls of the die. The encapsulant has a first surface and a second surface opposite to the first surface. The first surface is coplanar with the rear surface of the die. The second surface is located at a level height different from the active surface of the die. The dam structure is disposed on the active surface of the die. A top surface of the dam structure is substantially coplanar with the second surface of the encapsulant. The redistribution structure is over the encapsulant, the dam structure, and the die. The redistribution structure is electrically connected to the die.

公开(公告)号：US20190164888A1

公开(公告)日：2019-05-30

申请号：US16114237

申请日：2018-08-28

Applicant: Powertech Technology Inc.

Inventor： Shang-Yu Chang Chien ,  Hung-Hsin Hsu ,  Nan-Chun Lin

IPC: H01L23/522 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L25/18 ,  H01L25/00

Abstract: A package structure including a redistribution structure, a die, a plurality of conductive structures, a first insulating encapsulant, a chip stack, and a second insulating encapsulant. The die is disposed on and electrically connected to the redistribution structure. The conductive structures are disposed on and electrically connected to the redistribution structure. The conductive structures surround the die. The first insulating encapsulant encapsulates the die and the conductive structures. The first insulating structure includes a plurality of openings exposing top surfaces of the conductive structures. The chip stack is disposed on the first insulating encapsulant and the die. The chip stack is electrically connected to the conductive structures. The second insulating encapsulant encapsulates the chip stack.

公开(公告)号：US10269671B2

公开(公告)日：2019-04-23

申请号：US15647206

申请日：2017-07-11

Applicant: Powertech Technology Inc.

Inventor： Hung-Hsin Hsu ,  Nan-Chun Lin

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L27/146 ,  H01L21/56

Abstract: A manufacturing method of a package structure includes at least the following steps. A plurality of conductive connectors are formed on a circuit layer. The circuit layer includes a central region and a peripheral region electrically connected to the central region. A chip is disposed on the central region of the circuit layer. The chip includes an active surface at a distance from the circuit layer and a sensing area on the active surface. An encapsulant is formed on the circuit layer to encapsulate the chip and the conductive connectors. A redistribution layer is formed on the encapsulant to electrically connect the chip and the conductive connectors. The redistribution layer partially covers the chip and includes a window corresponding to the sensing area of the chip. A package structure is also provided.

公开(公告)号：US10170458B2

公开(公告)日：2019-01-01

申请号：US15782862

申请日：2017-10-13

Applicant: Powertech Technology Inc.

Inventor： Chi-An Wang ,  Hung-Hsin Hsu

IPC: H01L23/00 ,  H01L25/00 ,  H01L21/48 ,  H01L23/31 ,  H01L23/498 ,  H01L25/10 ,  H01L23/49 ,  H01L23/50 ,  H01L21/56 ,  H01L23/538 ,  H01L25/065 ,  H01L23/04 ,  H01L23/433

Abstract: A manufacturing method of a POP structure including at least the following steps is provided. A first package structure is formed and a second package structure is formed on the first package structure. The first package structure includes a circuit carrier and a die disposed on the circuit carrier. Forming the first package structure includes providing a conductive interposer on the circuit carrier, encapsulating the conductive interposer by an encapsulant and removing a portion of the encapsulant and the plate of the conductive interposer. The conductive interposer includes a plate, a plurality of conductive pillars and a conductive protrusion respectively extending from the plate to the circuit carrier and the die. The conductive protrusion disposed on the die, and the conductive pillars are electrically connected to the circuit carrier. The second package structure is electrically connected to the first package structure through the conductive interposer.

公开(公告)号：US10157828B2

公开(公告)日：2018-12-18

申请号：US15599477

申请日：2017-05-19

Applicant: Powertech Technology Inc.

Inventor： Hung-Hsin Hsu ,  Nan-Chun Lin

IPC: H01L23/522 ,  H01L23/31 ,  H01L23/00 ,  H01L25/04 ,  H01L21/56 ,  H01L25/00

Abstract: A chip package structure includes a semiconductor component, a plurality of conductive pillars, an encapsulant and a redistribution layer. The semiconductor component includes a plurality of pads. The conductive pillars are disposed on the pads, wherein each of the conductive pillars is a solid cylinder including a top surface and a bottom surface, and a diameter of the top surface is substantially the same as a diameter of the bottom surface. The encapsulant encapsulates the semiconductor component and the conductive pillars, wherein the encapsulant exposes the top surface of each of the conductive pillars. The redistribution layer is disposed on the encapsulant and electrically connected to the conductive pillars.