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公开(公告)号：US3673505A
公开(公告)日：1972-06-27
申请号：US3673505D
申请日：1970-11-13
Applicant: RCA CORP
Inventor： LIMBERG ALLEN LEROY
CPC classification number: H03D1/229
Abstract: Input signals are coupled in common to the emitter electrodes of a pair of transistors arranged in a differential amplifier configuration, and are synchronously detected by switching signals coupled to the respective transistor base electrodes. The coupling to the emitter electrodes is through a transistor arranged in a common-base amplifier construction, with the signals to be demodulated being applied to the amplifier transistor emitter electrode via an included stabilizing resistor.
Abstract translation: 输入信号共同耦合到以差分放大器配置布置的一对晶体管的发射极电极，并且通过耦合到各个晶体管基极的开关信号同步地检测。 与发射极电极的耦合是通过配置在共基放大器结构中的晶体管，被解调的信号经由包含的稳定电阻器施加到放大器晶体管发射极。
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公开(公告)号：US3646362A
公开(公告)日：1972-02-29
申请号：US3646362D
申请日：1970-04-30
Applicant: RCA CORP
Inventor： LIMBERG ALLEN LEROY
CPC classification number: H03D13/006
Abstract: A sample-and-hold circuit employs first and second transistors of the same conductivity type, having serially coupled collectorto-emitter current paths and including a feedback path coupling the collector of the first transistor to the base of the second transistor to provide a high-input impedance and a relatively low-output impedance circuit suitable for rapid updating of a hold capacitor. The circuit samples an applied signal when the first and second transistors are keyed into conduction by keying circuit means, and holds when these transistors are biased out of conduction. The circuit is particularly suited for application as a phase comparator.
Abstract translation: 采样和保持电路采用具有相同导电类型的第一和第二晶体管，具有串联耦合的集电极到发射极电流路径，并且包括将第一晶体管的集电极耦合到第二晶体管的基极的反馈路径， 高输入阻抗和适用于快速更新保持电容的相对低输出阻抗电路。 当第一和第二晶体管通过键控电路装置键入导通时，电路对施加的信号进行采样，并且当这些晶体管偏置导通时，该信号保持。 该电路特别适合用作相位比较器。
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公开(公告)号：US3629611A
公开(公告)日：1971-12-21
申请号：US3629611D
申请日：1969-12-29
Applicant: RCA CORP
Inventor： LIMBERG ALLEN LEROY
CPC classification number: H04B1/1653
Abstract: Average detection apparatus employing pulse-stretching techniques for increasing the energy content and compressing the dynamic pulse width range of a pulse train including randomly occurring, short duration, widely spaced pulses. The pulse train and a train of reference pulses are supplied to a bistable storage element to set and reset the element, respectively, to first and second output states. An average detector is coupled to the output of the storage element.
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公开(公告)号：US3555309A
公开(公告)日：1971-01-12
申请号：US3555309D
申请日：1967-11-03
Applicant: RCA CORP
Inventor： LIMBERG ALLEN LEROY
Abstract: An electrical circuit especially suited for fabrication using integrated circuit techniques including a common emitter transistor amplifier connected in cascade relation with a common collector transistor amplifier and interconnected with a pair of resistors of predetermined resistance ratio in a degenerative feedback loop so that the common emitter stage additionally provides a stabilized direct current voltage reference for the common collector stage.
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