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公开(公告)号：US20220245073A1
公开(公告)日：2022-08-04
申请号：US17677714
申请日：2022-02-22
Applicant: Rambus Inc.
Inventor： Thomas J. Giovannini , John Eric Linstadt , Catherine Chen
Abstract: A memory system supports single- and dual-memory-module configurations, both supporting point-to-point communication between a host (e.g., a memory controller) and the memory module or modules. Each memory module includes an address-buffer component, data-buffer components, and two sets of memory dies, each set termed a “timing rank,” that can be accessed independently. The one memory module is configured in a wide mode for the single-memory-module configuration, in which case both timing ranks work together, as a “package rank,” to communicate full-width data. Each of two memory modules are configured in a narrow mode for the dual-memory-module configuration, in which case one timing rank from each memory module communicates data in parallel to appear to the host as single package ranks. The data-buffer components support separate and configurable write and read delays for the different timing ranks on each module to provide read and write leveling within and between memory modules.
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公开(公告)号：US20160293239A1
公开(公告)日：2016-10-06
申请号：US15090399
申请日：2016-04-04
Applicant: Rambus Inc.
Inventor： Thomas J. Giovannini , Catherine Chen , Scott C. Best , John Eric Linstadt , Frederick A. Ware
CPC classification number: G06F11/079 , G06F11/073 , G06F11/0772 , G11C5/04 , G11C7/20 , G11C8/12 , G11C29/26 , G11C29/44
Abstract: During system initialization, each data buffer device and/or memory device on a memory module is configured with a unique (at least to the module) device identification number. In order to access a single device (rather than multiple buffers and/or memory devices), a target identification number is written to all of the devices using a command bus connected to all of the data buffer devices or memory devices, respectively. The devices whose respective device identification numbers do not match the target identification number are configured to ignore future command bus transactions (at least until the debug mode is turned off.) The selected device that is configured with a device identification number matching the target identification number is configured to respond to command bus transactions.
Abstract translation: 在系统初始化期间，存储器模块上的每个数据缓冲设备和/或存储器设备被配置为唯一（至少对于模块）设备标识号。 为了访问单个设备（而不是多个缓冲器和/或存储设备），使用分别连接到所有数据缓冲设备或存储设备的命令总线将目标识别号码写入所有设备。 各个设备标识号与目标识别号码不一致的设备被配置为忽略未来的命令总线事务（至少直到调试模式被关闭）。所选择的设备被配置有与目标识别号码相匹配的设备标识号 被配置为响应命令总线事务。
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公开(公告)号：US12155391B2
公开(公告)日：2024-11-26
申请号：US18070713
申请日：2022-11-29
Applicant: Rambus Inc.
Inventor： Panduka Wijetunga , Catherine Chen
Abstract: A phase-locked loop or delay locked loop provides a coarse alignment between an input clock and an output clock. A latch receiver circuit provides an indicator of a delay error between the input clock and the output clock. The delay error is used by a control circuit or state machine to adjust a fine delay that affects the output clock signal timing relative to the input clock signal. The fine delay is adjusted to minimize the timing difference between the output clock signal and the input clock signal.
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14.发明公开公开(公告)号：US20240095198A1
公开(公告)日：2024-03-21
申请号：US18480344
申请日：2023-10-03
Applicant: Rambus Inc.
Inventor： Thomas J. Giovannini , John Eric Linstadt , Catherine Chen
CPC classification number: G06F13/1689 , G06F13/1673 , G06F13/1678 , G06F13/4022 , G06F13/4265
Abstract: A memory system supports single- and dual-memory-module configurations, both supporting point-to-point communication between a host (e.g., a memory controller) and the memory module or modules. Each memory module includes an address-buffer component, data-buffer components, and two sets of memory dies, each set termed a “timing rank,” that can be accessed independently. The one memory module is configured in a wide mode for the single-memory-module configuration, in which case both timing ranks work together, as a “package rank,” to communicate full-width data. Each of two memory modules are configured in a narrow mode for the dual-memory-module configuration, in which case one timing rank from each memory module communicates data in parallel to appear to the host as single package ranks. The data-buffer components support separate and configurable write and read delays for the different timing ranks on each module to provide read and write leveling within and between memory modules.
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Patent Agency Ranking
公开(公告)号：US11275702B2
公开(公告)日：2022-03-15
申请号：US17021024
申请日：2020-09-15
Applicant: Rambus Inc.
Inventor： Thomas J. Giovannini , John Eric Linstadt , Catherine Chen
Abstract: A memory system supports single- and dual-memory-module configurations, both supporting point-to-point communication between a host (e.g., a memory controller) and the memory module or modules. Each memory module includes an address-buffer component, data-buffer components, and two sets of memory dies, each set termed a “timing rank,” that can be accessed independently. The one memory module is configured in a wide mode for the single-memory-module configuration, in which case both timing ranks work together, as a “package rank,” to communicate full-width data. Each of two memory modules are configured in a narrow mode for the dual-memory-module configuration, in which case one timing rank from each memory module communicates data in parallel to appear to the host as single package ranks. The data-buffer components support separate and configurable write and read delays for the different timing ranks on each module to provide read and write leveling within and between memory modules.
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公开(公告)号：US11068161B1
公开(公告)日：2021-07-20
申请号：US15645596
申请日：2017-07-10
Applicant: Rambus Inc.
Inventor： Catherine Chen , Thomas J. Giovannini , John Eric Linstadt
Abstract: In a memory module having a plurality of discrete memory die packages, an N-bit data interface and a command/address buffer, a memory access command and chip-select input signals are received within the command/address buffer. In response to the chip-select input signals, the command/address buffer outputs chip-select output signals greater in quantity than the chip-select input signals to exclusively enable one of a plurality of groups of the discrete memory die packages to respond to the memory access command, each of the plurality of groups of the discrete memory die packages having a collective data interface width less than the N-bit data interface width.
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公开(公告)号：US11016837B2
公开(公告)日：2021-05-25
申请号：US16183470
申请日：2018-11-07
Applicant: Rambus Inc.
Inventor： Thomas J. Giovannini , Catherine Chen , Scott C. Best , John Eric Linstadt , Frederick A. Ware
Abstract: During system initialization, each data buffer device and/or memory device on a memory module is configured with a unique (at least to the module) device identification number. In order to access a single device (rather than multiple buffers and/or memory devices), a target identification number is written to all of the devices using a command bus connected to all of the data buffer devices or memory devices, respectively. The devices whose respective device identification numbers do not match the target identification number are configured to ignore future command bus transactions (at least until the debug mode is turned off.) The selected device that is configured with a device identification number matching the target identification number is configured to respond to command bus transactions.
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18.发明授权公开(公告)号：US10789185B2
公开(公告)日：2020-09-29
申请号：US15701698
申请日：2017-09-12
Applicant: Rambus Inc.
Inventor： Thomas J. Giovannini , John Eric Linstadt , Catherine Chen
Abstract: A memory system supports single- and dual-memory-module configurations, both supporting point-to-point communication between a host (e.g., a memory controller) and the memory module or modules. Each memory module includes an address-buffer component, data-buffer components, and two sets of memory dies, each set termed a “timing rank,” that can be accessed independently. The one memory module is configured in a wide mode for the single-memory-module configuration, in which case both timing ranks work together, as a “package rank,” to communicate full-width data. Each of two memory modules are configured in a narrow mode for the dual-memory-module configuration, in which case one timing rank from each memory module communicates data in parallel to appear to the host as single package ranks. The data-buffer components support separate and configurable write and read delays for the different timing ranks on each module to provide read and write leveling within and between memory modules.
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19.发明申请公开(公告)号：US20180081833A1
公开(公告)日：2018-03-22
申请号：US15701698
申请日：2017-09-12
Applicant: Rambus Inc.
Inventor： Thomas J. Giovannini , John Eric Linstadt , Catherine Chen
Abstract: A memory system supports single- and dual-memory-module configurations, both supporting point-to-point communication between a host (e.g., a memory controller) and the memory module or modules. Each memory module includes an address-buffer component, data-buffer components, and two sets of memory dies, each set termed a “timing rank,” that can be accessed independently. The one memory module is configured in a wide mode for the single-memory-module configuration, in which case both timing ranks work together, as a “package rank,” to communicate full-width data. Each of two memory modules are configured in a narrow mode for the dual-memory-module configuration, in which case one timing rank from each memory module communicates data in parallel to appear to the host as single package ranks. The data-buffer components support separate and configurable write and read delays for the different timing ranks on each module to provide read and write leveling within and between memory modules.
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