公开(公告)号：US20190267351A1

公开(公告)日：2019-08-29

申请号：US16152237

申请日：2018-10-04

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Eun Jung JO ,  Han KIM ,  Yoon Seok SEO

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31

Abstract: A fan-out semiconductor package includes a first core member including a first through-hole, a first semiconductor chip disposed in the first through-hole of the first core member, a first encapsulant configured to encapsulate at least a portion of the first semiconductor chip, a first connection member disposed on the first semiconductor chip and including a first redistribution layer, a second core member adhered to a lower surface of the first connection member and including a second through-hole, a second semiconductor chip disposed in the second through-hole of the second core member, a second encapsulant configured to encapsulate the second semiconductor chip, the second core member, and the first connection member, a second connection member disposed on the second semiconductor chip and including a second redistribution layer, and a connection via penetrating through the second core member and configured to electrically connect the first redistribution layer and the second redistribution layer.

公开(公告)号：US20190164893A1

公开(公告)日：2019-05-30

申请号：US15940104

申请日：2018-03-29

Applicant: Samsung Electro-Mechanics, Co., Ltd.

Inventor： Han KIM ,  Eun Jung JO ,  Jung Ho SHIM

IPC: H01L23/538 ,  H01L23/498 ,  H01L23/367 ,  H01L23/31 ,  H01L25/10

Abstract: A semiconductor package includes: an interposer having a first surface and a second surface and including a first redistribution layer; a semiconductor chip having an active surface having connection electrodes disposed thereon and an inactive surface and disposed on the interposer so that the inactive surface faces the second surface of the interposer; an encapsulant disposed on the second surface of the interposer, including a photosensitive insulating material, and having a first region covering the semiconductor chip and a second region positioned around the semiconductor chip; and a second redistribution layer including second vias penetrating through the first region of the encapsulant and connected to the connection electrodes, through-vias penetrating through the second region of the encapsulant and connected to the first redistribution layer, and second wiring patterns disposed on the encapsulant and having integrated structures with the second vias and the through-vias.

公开(公告)号：US20190096824A1

公开(公告)日：2019-03-28

申请号：US15923708

申请日：2018-03-16

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Kang Heon HUR ,  Jong Man KIM ,  Kyung Ho LEE ,  Han KIM

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/373

Abstract: A semiconductor package includes a wiring portion including an insulating layer, conductive patterns disposed on the insulating layer, and conductive vias penetrating through the insulating layer and connected to the conductive patterns, a semiconductor chip disposed on the wiring portion, an encapsulant disposed on the wiring portion and encapsulating at least a portion of the semiconductor chip, and a metal layer disposed on the semiconductor chip and the encapsulant and having a thickness of 10 μm to 70 μm.

公开(公告)号：US20180233432A1

公开(公告)日：2018-08-16

申请号：US15955178

申请日：2018-04-17

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Han KIM ,  Young Gwan KO ,  Kang Heon HUR ,  Kyung Moon JUNG ,  Sung Han KIM

IPC: H01L23/48 ,  H01L23/31 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538

Abstract: An electronic component package may include: a redistribution layer including a first insulating layer, a first conductive pattern disposed on the first insulating layer, and a first via connected to the first conductive pattern while penetrating through the first insulating layer; an electronic component disposed on the redistribution layer; and an encapsulant encapsulating the electronic component. The first via has a horizontal cross-sectional shape in which a distance between first and second edge points of the first via in a first direction passing through the center of the first via and the first and second edge points thereof is shorter than that between third and fourth edge points of the first via in a second direction perpendicular to the first direction and passing through the center of the first via and the third and fourth points thereof.

公开(公告)号：US20180174994A1

公开(公告)日：2018-06-21

申请号：US15666073

申请日：2017-08-01

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Seong Hee CHOI ,  Han KIM ,  Dae Hyun PARK ,  Mi Ja HAN

IPC: H01L23/00 ,  H01L23/538 ,  H01L23/13

CPC classification number: H01L24/20 ,  H01L21/56 ,  H01L21/76802 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/49838 ,  H01L23/5389 ,  H01L2924/19011 ,  H01L2924/19042 ,  H01L2924/3511

Abstract: A fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole; an encapsulant encapsulating at least portions of the first connection member and the semiconductor chip; and a second connection member disposed on the first connection member and the semiconductor chip. The first connection member and the second connection member include, respectively, redistribution layers electrically connected to the connection pads of the semiconductor chip, the second connection member includes a coil pattern layer electrically connected to the connection pads of the semiconductor chip, and at least one of the first connection member and the second connection member includes a dummy pattern layer.

公开(公告)号：US20180138083A1

公开(公告)日：2018-05-17

申请号：US15668121

申请日：2017-08-03

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Han KIM ,  Mi Ja HAN ,  Dae Hyun PARK

IPC: H01L21/768 ,  H01L21/48 ,  H01L21/56 ,  H01L21/02 ,  H01L23/00

Abstract: A fan-out semiconductor package includes a first connection member having a through-hole, first and second semiconductor chips disposed in the through-hole, an encapsulant encapsulating at least portions of the first connection member, the first semiconductor chip, and the second semiconductor chip, and a second connection member disposed on the first connection member and on active surfaces of the first semiconductor chip and the second semiconductor chip. A redistribution layer of the second connection member is respectively connected to both the first and second connection pads through first and second conductors, and the second conductor has a height greater than that of the first conductor.

公开(公告)号：US20180138029A1

公开(公告)日：2018-05-17

申请号：US15673149

申请日：2017-08-09

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Han KIM ,  Mi Ja HAN ,  Dae Hyun PARK ,  Sang Jong LEE ,  Seong Hee CHOI

IPC: H01L21/02 ,  H01L21/56 ,  H01L21/48 ,  H01L21/768 ,  H01L23/00

CPC classification number: H01L21/0231 ,  H01L21/486 ,  H01L21/568 ,  H01L21/76841 ,  H01L21/76897 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/19 ,  H01L2224/16225 ,  H01L2224/19 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole of the first connection member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first connection member and the inactive surface of the semiconductor chip; and a second connection member disposed on the first connection member and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads. The first connection member includes a first electromagnetic interference (EMI) blocking part surrounding side surfaces of the semiconductor chip, the second connection member includes a second EMI blocking part surrounding the redistribution layer, and the first EMI blocking part and the second EMI blocking part are connected to each other.

公开(公告)号：US20180012700A1

公开(公告)日：2018-01-11

申请号：US15619974

申请日：2017-06-12

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Sang Jong LEE ,  Su Bong JANG ,  Han KIM ,  Min Ki JUNG

IPC: H01F27/30 ,  H01F27/32 ,  H01F5/04 ,  H03H7/38 ,  H01F27/28

Abstract: A coil component may include a body including a plurality of insulating layers having coil patterns disposed on the plurality of insulating layers. The coil pattern may include a coil portion, a leading portion disposed on one side of the insulating layer, and a connection portion connecting the coil portion and the leading portion, a pattern line of the coil portion may have an arc shape, and the connection portion may be formed in a tangent line direction of the coil portion from one end of the leading portion.

公开(公告)号：US20170365568A1

公开(公告)日：2017-12-21

申请号：US15454416

申请日：2017-03-09

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Young Min BAN ,  Han KIM ,  Kyung Moon JUNG

IPC: H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L23/31

CPC classification number: H01L24/06 ,  H01L23/3128 ,  H01L23/3171 ,  H01L23/5226 ,  H01L23/5283 ,  H01L24/03 ,  H01L24/14 ,  H01L24/20 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05008 ,  H01L2224/05017 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/12105 ,  H01L2224/13021 ,  H01L2224/18 ,  H01L2224/20 ,  H01L2224/73204 ,  H01L2924/15153 ,  H01L2924/171 ,  H01L2924/19105 ,  H05K1/185

Abstract: A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having a connection pad disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip; and a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip, wherein the first interconnection member and the second interconnection member include, respectively, redistribution layers electrically connected to the connection pad, the semiconductor chip includes a passivation layer having an opening exposing at least a portion of the connection pad, the redistribution layer of the second interconnection member is connected to the connection pad through a via, and the via covers at least a portion of the passivation layer.

公开(公告)号：US20170287853A1

公开(公告)日：2017-10-05

申请号：US15278248

申请日：2016-09-28

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Han KIM ,  Mi Ja HAN ,  Kang Heon HUR ,  Young Gwan KO

IPC: H01L23/64 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L23/3114 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5283 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/642 ,  H01L2224/02379 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/24195 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/19106 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: The fan-out semiconductor package includes: a semiconductor chip having an active surface having a connection pad disposed thereon and an inactive surface disposed to oppose the active surface; a first capacitor disposed adjacently to the semiconductor chip; an encapsulant at least partially encapsulating the first connection member and the semiconductor chip; a first connection member disposed on the encapsulant, the first capacitor, and the semiconductor chip, and a second capacitor disposed on the other surface of the first connection member opposing one surface of the first connection member on which the semiconductor chip is disposed, wherein the first connection member includes a redistribution layer electrically connected to the connection pad of the semiconductor chip, the first capacitor, and the second capacitor, and the first capacitor and the second capacitor are electrically connected to the connection pad through a common power wiring of the redistribution layer.