中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

21 records (took 0.014 seconds)

    Laminate structures with hole plugs and methods of forming laminate structures with hole plugs
    11.
    发明授权
    Laminate structures with hole plugs and methods of forming laminate structures with hole plugs 有权

    公开(公告)号：US11246226B2

    公开(公告)日：2022-02-08

    申请号：US16298896

    申请日：2019-03-11

    Applicant: Sanmina Corporation

    Inventor： Shinichi Iketani ,  Dale Kersten

    IPC: H01K3/10 ,  H05K3/42 ,  H05K1/11 ,  H05K3/00

    Abstract: Laminate structures including hole plugs, and methods for forming a hole plug in a laminate structure are provided. A laminate structure may be formed with at least a dielectric layer and a first conductive foil on a first side of the dielectric layer. A blind hole may be formed in the laminate structure extending toward the first conductive foil from a second side of the dielectric layer and at least partially through the dielectric layer, the blind hole including a hole depth to hole diameter aspect ratio of less than ten (10) to one (1). Via fill ink may be disposed in the blind hole, and the via fill ink may be dried and/or cured to form a hole plug.

    LAMINATE STRUCTURES WITH HOLE PLUGS AND METHODS OF FORMING LAMINATE STRUCTURES WITH HOLE PLUGS
    12.
    发明申请
    LAMINATE STRUCTURES WITH HOLE PLUGS AND METHODS OF FORMING LAMINATE STRUCTURES WITH HOLE PLUGS 审中-公开

    公开(公告)号：US20190208645A1

    公开(公告)日：2019-07-04

    申请号：US16298896

    申请日：2019-03-11

    Applicant: Sanmina Corporation

    Inventor： Shinichi Iketani ,  Dale Kersten

    IPC: H05K3/42 ,  H05K1/11

    CPC classification number: H05K3/429 ,  H05K1/116 ,  H05K3/0094 ,  Y10T29/49165

    Abstract: Laminate structures including hole plugs, and methods for forming a hole plug in a laminate structure are provided. A laminate structure may be formed with at least a dielectric layer and a first conductive foil on a first side of the dielectric layer. A blind hole may be formed in the laminate structure extending toward the first conductive foil from a second side of the dielectric layer and at least partially through the dielectric layer, the blind hole including a hole depth to hole diameter aspect ratio of less than ten (10) to one (1). Via fill ink may be disposed in the blind hole, and the via fill ink may be dried and/or cured to form a hole plug.

    Simultaneous and selective wide gap partitioning of via structures using plating resist
    13.
    发明授权
    Simultaneous and selective wide gap partitioning of via structures using plating resist 有权

    公开(公告)号：US10123432B2

    公开(公告)日：2018-11-06

    申请号：US15723135

    申请日：2017-10-02

    Applicant: SANMINA CORPORATION

    Inventor： Shinichi Iketani ,  Dale Kersten

    IPC: H05K3/42 ,  H05K1/11 ,  H05K1/02

    Abstract: A multilayer printed circuit board is provided having a first dielectric layer and a first plating resist selectively positioned in the first dielectric layer. A second plating resist may be selectively positioned in the first dielectric layer or a second dielectric layer, the second plating resist separate from the first plating resist. A through hole extends through the first dielectric layer, the first plating resist, and the second plating resist. An interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist. This forms a partitioned plated through hole having a first via segment electrically isolated from a second via segment.

    SIMULTANEOUS AND SELECTIVE WIDE GAP PARTITIONING OF VIA STRUCTURES USING PLATING RESIST
    16.
    发明申请
    SIMULTANEOUS AND SELECTIVE WIDE GAP PARTITIONING OF VIA STRUCTURES USING PLATING RESIST 审中-公开

    公开(公告)号：US20200383204A1

    公开(公告)日：2020-12-03

    申请号：US16883671

    申请日：2020-05-26

    Applicant: Sanmina Corporation

    Inventor： Shinichi Iketani ,  Dale Kersten ,  George Dudnikov, JR.

    IPC: H05K1/11 ,  H05K1/03 ,  H05K3/42

    Abstract: A multilayer printed circuit board is provided having a first dielectric layer and a first plating resist selectively positioned in the first dielectric layer. A second plating resist may be selectively positioned in the first dielectric layer or a second dielectric layer, the second plating resist separate from the first plating resist. A through hole extends through the first dielectric layer, the first plating resist, and the second plating resist. An interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist. This forms a partitioned plated through hole having a first via segment electrically isolated from a second via segment.

    Simultaneous and selective wide gap partitioning of via structures using plating resist
    18.
    发明授权
    Simultaneous and selective wide gap partitioning of via structures using plating resist 有权

    公开(公告)号：US10667390B2

    公开(公告)日：2020-05-26

    申请号：US15723086

    申请日：2017-10-02

    Applicant: SANMINA CORPORATION

    Inventor： Shinichi Iketani ,  Dale Kersten ,  George Dudnikov, Jr.

    IPC: H05K1/11 ,  H05K1/03 ,  H05K3/42

    Abstract: A multilayer printed circuit board is provided having a first dielectric layer and a first plating resist selectively positioned in the first dielectric layer. A second plating resist may be selectively positioned in the first dielectric layer or a second dielectric layer, the second plating resist separate from the first plating resist. A through hole extends through the first dielectric layer, the first plating resist, and the second plating resist. An interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist. This forms a partitioned plated through hole having a first via segment electrically isolated from a second via segment.

Patent Agency Ranking