公开(公告)号：US11726543B2

公开(公告)日：2023-08-15

申请号：US17111373

申请日：2020-12-03

Applicant: STMICROELECTRONICS S.r.l. ,  STMicroelectronics International N.V.

Inventor： Nitin Chawla ,  Anuj Grover ,  Giuseppe Desoli ,  Kedar Janardan Dhori ,  Thomas Boesch ,  Promod Kumar

IPC: G06F1/3234 ,  G05F3/24 ,  G06F1/3287 ,  G06F15/78 ,  G11C11/413 ,  G11C5/14 ,  G11C11/417 ,  G06F1/26

CPC classification number: G06F1/3275 ,  G05F3/24 ,  G06F1/3287 ,  G06F15/7821 ,  G11C11/413

Abstract: Systems and devices are provided to enable granular control over a retention or active state of each of a plurality of memory circuits, such as a plurality of memory cell arrays, within a memory. Each respective memory array of the plurality of memory arrays is coupled to a respective ballast driver and a respective active memory signal switch for the respective memory array. One or more voltage regulators are coupled to a ballast driver gate node and to a bias node of at least one of the respective memory arrays. In operation, the respective active memory signal switch for a respective memory array causes the respective memory array to transition between an active state for the respective memory array and a retention state for the respective memory array.