公开(公告)号：US10706915B2

公开(公告)日：2020-07-07

申请号：US16351773

申请日：2019-03-13

Applicant: STMicroelectronics International N.V.

Inventor： Abhishek Pathak ,  Tanmoy Roy ,  Shishir Kumar

IPC: G11C7/00 ,  G11C11/412 ,  G11C7/14 ,  G11C11/419 ,  G11C8/08 ,  G11C11/413 ,  G11C11/418

Abstract: A memory device includes first and second dummy word line portions. A dummy word line driver drives the first dummy word line portion. A voltage dropping circuit causes a voltage on the second dummy word line to be less than a voltage on the first dummy word line. At least one dummy memory cell is coupled to the second dummy word line portion, remains in standby until assertion of the second dummy word line, and performs a dummy cycle in response to assertion of the second dummy word line. A reset signal generation circuit generates a reset signal in response to completion of a dummy cycle by the at least one dummy memory cell. An internal clock signal is generated from an external clock signal and the reset signal and is used in performing a read and/or write cycle to a memory array.

公开(公告)号：US20150365080A1

公开(公告)日：2015-12-17

申请号：US14304357

申请日：2014-06-13

Applicant: STMicroelectronics International N.V.

Inventor： Shishir Kumar ,  Tanmoy Roy

IPC: H03K5/01 ,  G11C8/18

CPC classification number: H03K5/01 ,  G11C7/222 ,  G11C8/18

Abstract: According to an embodiment, a method of generating a clock pulse includes receiving a leading edge at a clock input at a time when an enable signal is active, generating an edge at a clock output based on the received leading edge at the clock input, latching a logic value corresponding to the edge at the clock output, preventing changes at the clock input from affecting the latched logic value after the logic value is latched, resetting the latched logic value after a first delay time, and maintaining the reset logic value until a second edge is received at the clock input. The second edge at the clock input matches the leading edge at the clock input.

Abstract translation: 根据实施例，一种产生时钟脉冲的方法包括在使能信号有效时在时钟输入端处接收前沿，在时钟输出端基于接收到的前沿产生时钟输出的边沿，锁存 对应于时钟输出端的逻辑值，防止在逻辑值被锁存之后时钟输入的变化影响锁存的逻辑值，在第一延迟时间之后复位锁存的逻辑值，并保持复位逻辑值直到 在时钟输入端接收第二个边沿。 时钟输入端的第二个边沿与时钟输入端的前沿匹配。

公开(公告)号：US11742045B2

公开(公告)日：2023-08-29

申请号：US17222119

申请日：2021-04-05

Applicant: STMicroelectronics International N.V.

Inventor： Rohit Bhasin ,  Shishir Kumar ,  Tanmoy Roy ,  Deepak Kumar Bihani

IPC: G11C29/38 ,  G11C29/14

CPC classification number: G11C29/38 ,  G11C29/14

Abstract: A decoder decodes a memory address and selectively drives a select line (such as a word line or mux line) of a memory. An encoding circuit encodes the data on select lines to generate an encoded address. The encoded address and the memory address are compared by a comparison circuit to generate a test result signal which is indicative of whether the decoder is operating properly. To test the comparison circuit for proper operation, a subset of an MBIST scan routine causes the encoded address to be blocked from the comparison circuit and a force signal to be applied in its place. A test signal from the scan routine and the force signal are then compared by the comparison circuit, with the test result signal generated from the comparison being indicative of whether the comparison circuit itself is operating properly.

公开(公告)号：US10283191B1

公开(公告)日：2019-05-07

申请号：US15917227

申请日：2018-03-09

Applicant: STMicroelectronics International N.V.

Inventor： Abhishek Pathak ,  Tanmoy Roy ,  Shishir Kumar

IPC: G11C7/00 ,  G11C11/412 ,  G11C7/14 ,  G11C11/419

Abstract: Disclosed herein is a memory circuit including a dummy word line driver driving a dummy word line, dummy memory cells coupled to a dummy bit line and a dummy complementary bit line, and a transmission gate coupled to the dummy word line to pass a word line signal from the dummy word line driver to an input of the dummy memory cells. A transistor is coupled to the dummy word line between the transmission gate and a pair of pass gates of a given one of the dummy memory cells closest to the transmission gate along the dummy word line. A reset signal output is coupled to the dummy complementary bit line. The transistor serves to lower a voltage on the dummy word line, and a reset signal indicating an end of a measured dummy cycle is generated at the reset signal output.

公开(公告)号：US20190035454A1

公开(公告)日：2019-01-31

申请号：US16025647

申请日：2018-07-02

Applicant: STMicroelectronics International N.V.

Inventor： Dhori Kedar Janardan ,  Abhishek Pathak ,  Shishir Kumar

IPC: G11C11/417

Abstract: A first transistor has a first conduction terminal coupled to a second bit line, a second conduction terminal coupled to a bit line node, and a control terminal biased by a second control signal. A second transistor has a first conduction terminal coupled to a second complementary bit line, a second conduction terminal coupled to a complementary bit line node, and a control terminal biased by the second control signal. A first replica transistor has a first conduction terminal coupled to the second bit line, a second conduction terminal coupled to the complementary bit line node, and a control terminal biased such that the first replica transistor is off. A second replica transistor has a first conduction terminal coupled to the second complementary bit line, a second conduction terminal coupled to the bit line node, and a control terminal biased such that the second replica transistor is off.

公开(公告)号：US09324414B2

公开(公告)日：2016-04-26

申请号：US13949449

申请日：2013-07-24

Applicant: STMicroelectronics International N.V.

Inventor： Nishu Kohli ,  Shishir Kumar

IPC: G11C8/16 ,  G11C11/419 ,  G11C7/22

CPC classification number: G11C11/419 ,  G11C7/227

Abstract: A write is performed to a first cell of a memory at a first row and column during a first memory access cycle. A memory access operation is made to a second cell at a second row and column during an immediately following second memory access cycle. If the memory access is a read from the second cell and the second row is the same as the first row, or if the memory access is a write to the second cell and the second row is the same as the first row and the second column is different than the first column, then a simultaneous operation is performed during the second memory access cycle. The simultaneous operation is an access of the second cell (for read or write) and a re-write of data from the first memory access cycle write operation back to the first cell.

Abstract translation: 在第一存储器访问周期期间在第一行和列处对存储器的第一单元执行写入。 在紧接着的第二存储器访问周期期间，在第二行和列处对第二单元进行存储器存取操作。 如果存储器访问是从第二单元读取并且第二行与第一行相同，或者如果存储器访问是对第二单元的写入，并且第二行与第一行和第二列相同 与第一列不同，则在第二存储器访问周期期间执行同时操作。 同时操作是第二单元（用于读取或写入）的访问以及从第一存储器访问周期写入操作重新写入数据到第一单元。

公开(公告)号：US20140204656A1

公开(公告)日：2014-07-24

申请号：US13746395

申请日：2013-01-22

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Shishir Kumar

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C8/08 ,  G11C11/418

Abstract: A memory cell includes a latch having a true data node and a complement data node, a true bitline, a complement bitline, a first access transistor coupled between the true bitline and the true data node, and a second access transistor coupled between the complement bitline and the complement data node. A wordline driver circuit includes a true wordline coupled to control the first access transistor and a complement wordline coupled to control the second access transistor. The wordline driver generates control signals on the true and complement wordlines to access the memory cell by: actuating the first access transistor while the second access transistor is not actuated and then actuating the second access transistor while the first access transistor is not actuated. The bitlines and wordlines are supplied from different sets of power supply voltages, with the bitline high supply voltage being less than the wordline high supply voltage.

Abstract translation: 存储单元包括具有真实数据节点和补码数据节点的锁存器，真位线，补码位线，耦合在真位线和真数据节点之间的第一存取晶体管，以及耦合在补码位线 和补码数据节点。 字线驱动器电路包括耦合以控制第一存取晶体管的真字字线和耦合以控制第二存取晶体管的补码字线。 字线驱动器通过在第二存取晶体管未被致动的同时致动第一存取晶体管，然后在第一存取晶体管未被致动时致动第二存取晶体管，在真和补码字线上产生访问存储单元的控制信号。 位线和字线由不同的电源电压供应，位线高电源电压小于字线高电源电压。

公开(公告)号：US11889675B2

公开(公告)日：2024-01-30

申请号：US18052514

申请日：2022-11-03

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Tushar Sharma ,  Tanmoy Roy ,  Shishir Kumar

IPC: G11C7/10 ,  H10B10/00 ,  G11C5/06 ,  G11C11/412 ,  H01L27/02 ,  G11C8/16 ,  G11C11/417

CPC classification number: H10B10/12 ,  G11C5/063 ,  G11C8/16 ,  G11C11/412 ,  G11C11/417 ,  H01L27/0207

Abstract: The present disclosure is directed to a circuit layout of a dual port static random-access-memory (SRAM) cell. The memory cell includes active regions in a substrate, with polysilicon gate electrodes on the active regions to define transistors of the memory cell. The eight transistor (8T) memory cell layout includes a reduced aspect ratio and non-polysilicon bit line discharge path routing by positioning an active region for the first port opposite an active region for the second port and consolidating power line nodes at a central portion of the memory cell.

公开(公告)号：US10037794B1

公开(公告)日：2018-07-31

申请号：US15660371

申请日：2017-07-26

Applicant: STMicroelectronics International N.V.

Inventor： Dhori Kedar Janardan ,  Abhishek Pathak ,  Shishir Kumar

IPC: G11C5/06 ,  G11C11/417

CPC classification number: G11C11/417 ,  G11C5/14 ,  G11C7/227 ,  G11C11/419 ,  G11C2207/002

Abstract: A first transistor has a first conduction terminal coupled to a second bit line, a second conduction terminal coupled to a bit line node, and a control terminal biased by a second control signal. A second transistor has a first conduction terminal coupled to a second complementary bit line, a second conduction terminal coupled to a complementary bit line node, and a control terminal biased by the second control signal. A first replica transistor has a first conduction terminal coupled to the second bit line, a second conduction terminal coupled to the complementary bit line node, and a control terminal biased such that the first replica transistor is off. A second replica transistor has a first conduction terminal coupled to the second complementary bit line, a second conduction terminal coupled to the bit line node, and a control terminal biased such that the second replica transistor is off.

公开(公告)号：US09165642B2

公开(公告)日：2015-10-20

申请号：US13746395

申请日：2013-01-22

Applicant: STMicroelectronics International N.V.

Inventor： Shishir Kumar

IPC: G11C11/00 ,  G11C11/419 ,  G11C8/08 ,  G11C11/418

CPC classification number: G11C11/419 ,  G11C8/08 ,  G11C11/418

Abstract: A memory cell includes a latch having a true data node and a complement data node, a true bitline, a complement bitline, a first access transistor coupled between the true bitline and the true data node, and a second access transistor coupled between the complement bitline and the complement data node. A wordline driver circuit includes a true wordline coupled to control the first access transistor and a complement wordline coupled to control the second access transistor. The wordline driver generates control signals on the true and complement wordlines to access the memory cell by: actuating the first access transistor while the second access transistor is not actuated and then actuating the second access transistor while the first access transistor is not actuated. The bitlines and wordlines are supplied from different sets of power supply voltages, with the bitline high supply voltage being less than the wordline high supply voltage.

Abstract translation: 存储单元包括具有真实数据节点和补码数据节点的锁存器，真位线，补码位线，耦合在真位线和真数据节点之间的第一存取晶体管，以及耦合在补码位线 和补码数据节点。 字线驱动器电路包括耦合以控制第一存取晶体管的真字字线和耦合以控制第二存取晶体管的补码字线。 字线驱动器通过在第二存取晶体管未被致动的同时致动第一存取晶体管，然后在第一存取晶体管未被致动时致动第二存取晶体管，在真和补码字线上产生访问存储单元的控制信号。 位线和字线由不同的电源电压供应，位线高电源电压小于字线高电源电压。