公开(公告)号：US10996266B2

公开(公告)日：2021-05-04

申请号：US16536462

申请日：2019-08-09

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan Srinivasan ,  Rajesh Narwal ,  Srinivas Dhulipalla

IPC: G01R31/28

Abstract: Circuits and methods for testing voltage monitor circuits are provided. In an embodiment, an integrated circuit (IC) includes power management unit (PMU), a set-reset (S-R) latch circuit, a multiplexer, and an AND gate circuit. A voltage monitor circuit of the PMU generates an output signal based on a difference between a received reference voltage and a received sense voltage from a functional supply. A power on reset (PoR) generator of the PMU generates a PoR signal based on a power up condition of the PMU. The S-R latch circuit generates an enable signal based on the output signal of the comparator circuit and the PoR signal. The multiplexer passes-through the output signal of the comparator circuit during a functional condition of the PMU. The AND gate circuit generates an enable signal based on an output of the multiplexer and an output of the S-R latch circuit.

公开(公告)号：US20210041496A1

公开(公告)日：2021-02-11

申请号：US16536462

申请日：2019-08-09

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan Srinivasan ,  Rajesh Narwal ,  Srinivas Dhulipalla

IPC: G01R31/28

Abstract: Circuits and methods for testing voltage monitor circuits are provided. In an embodiment, an integrated circuit (IC) includes power management unit (PMU), a set-reset (S-R) latch circuit, a multiplexer, and an AND gate circuit. A voltage monitor circuit of the PMU generates an output signal based on a difference between a received reference voltage and a received sense voltage from a functional supply. A power on reset (PoR) generator of the PMU generates a PoR signal based on a power up condition of the PMU. The S-R latch circuit generates an enable signal based on the output signal of the comparator circuit and the PoR signal. The multiplexer passes-through the output signal of the comparator circuit during a functional condition of the PMU. The AND gate circuit generates an enable signal based on an output of the multiplexer and an output of the S-R latch circuit.

公开(公告)号：US10386411B2

公开(公告)日：2019-08-20

申请号：US15684334

申请日：2017-08-23

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan Srinivasan ,  Manish Sharma

IPC: G01R31/317 ,  G01R31/3185

Abstract: A JTAG interface in an IC includes a test mode select (TMS) pin receiving a TMS signal, a testing test access port (TAP) having a TMS signal input, a debugging test access port (TAP) having a TMS signal and glue logic coupled to receive a first output from the testing TAP and a second output from the debugging TAP. A flip-flop receives input from the testing TAP and the debugging TAP through the glue logic. A first AND gate has output coupled to the TMS signal input of the debugging TAP, and receives input from an output of the flip-flop and the TMS signal. An inverter has an input coupled to receive input from the flip-flop. A second AND gate has output coupled to the TMS signal input of the testing TAP, and receives input from the TMS signal and output of the inverter.

公开(公告)号：US20190094301A1

公开(公告)日：2019-03-28

申请号：US15712778

申请日：2017-09-22

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan Srinivasan ,  Satinder Singh Malhi

IPC: G01R31/3185 ,  G01R31/04 ,  H01L21/66

Abstract: A scan chain collects scan chain data from testing of a functional circuit and outputs a scan chain signal containing the scan chain data. A voltage monitor circuit operates to compare a supply voltage against a threshold and assert a reset signal when the supply voltage crosses the threshold. The reset signal resets a flip flop circuit whose output signal controls operation of a logic circuit that blocks passage of the scan chain signal to an integrated circuit probe pad and instead applies a constant logic signal to the probe pad indicating a voltage monitoring error.

公开(公告)号：US20190064268A1

公开(公告)日：2019-02-28

申请号：US16170479

申请日：2018-10-25

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan Srinivasan ,  Nimit Endlay ,  Balwinder Singh Soni

IPC: G01R31/317 ,  G01R31/3193 ,  G01R31/3177 ,  G06F11/25 ,  G06F11/26 ,  G06F11/27

CPC classification number: G01R31/31727 ,  G01R31/31722 ,  G01R31/31723 ,  G01R31/31724 ,  G01R31/3177 ,  G01R31/31922 ,  G01R31/31937 ,  G06F11/25 ,  G06F11/26 ,  G06F11/27

Abstract: A test circuit is operable in ATPG mode and LBIST mode. The test circuit includes a clock selection circuit. The clock selection circuit includes clock logic circuitry to receive an LBIST mode signal and an ATPG mode signal and to generate an indication of whether the test circuit is operating in either the ATPG mode or the LBIST mode, a multiplexing circuit to receive an ATPG clock and a functional clock as input and output a selected one of the ATPG clock and the functional clock, and a clock gate circuit enabled in response to enable signals. The enable signals are an inverse of a selected one of the ATPG clock and the functional clock. The clock gate circuit receives the indication of whether the test circuit is operating in either the ATPG mode or the LBIST mode and generates a test clock as a function of the indication.

公开(公告)号：US10151797B2

公开(公告)日：2018-12-11

申请号：US15223061

申请日：2016-07-29

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan Srinivasan ,  Tripti Gupta

IPC: G01R31/3185

Abstract: A logic built-in self-test (LBIST) circuit implements a pipeline scan enable launch on shift (LOS) feature. A first scan chain flip-flop has a scan enable input configured to receive a first scan enable signal. A logic circuit has a first input coupled to a data output of the first scan chain flip-flop and a second input coupled to receive the first scan enable signal. A second scan chain flip-flop has a scan input coupled to a scan output of the first scan chain flip-flop. A scan enable input of the second scan chain flip-flop is coupled to receive a second scan enable signal generated at an output of the logic circuit. The first and second scan chain flip-flops are clocked by a same clock signal.

公开(公告)号：US20180080987A1

公开(公告)日：2018-03-22

申请号：US15268848

申请日：2016-09-19

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan Srinivasan ,  Nimit Endlay ,  Balwinder Singh Soni

IPC: G01R31/317 ,  G01R31/3177

CPC classification number: G01R31/31727 ,  G01R31/31722 ,  G01R31/31723 ,  G01R31/31724 ,  G01R31/3177 ,  G01R31/31937 ,  G06F11/25 ,  G06F11/26 ,  G06F11/27

Abstract: A test circuit receives LBIST and ATPG mode signals, and generates a first output as high when in ATPG or LBIST, and a second output as low when in ATPG or LBIST. A multiplexing circuit receives an ATPG clock and functional clock, and outputs one. A clock gate circuit includes a first latch receiving the second output, and an enable input receiving an inverse of the ATPG clock or functional clock. A second latch receives the first output, and has an enable input receiving the inverse of the ATPG clock or functional clock. The clock gate circuit includes a first AND gate receiving output of the first latch and ATPG clock or functional clock, a second AND gate receiving output of the second latch and the ATPG clock or LBIST clock, and an OR gate receiving outputs of the first and second AND gates, and generating a test clock.

公开(公告)号：US20180013418A1

公开(公告)日：2018-01-11

申请号：US15615178

申请日：2017-06-06

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan Srinivasan ,  Srinivas Dhulipalla

IPC: H03K17/22 ,  H03K19/20 ,  H03K5/19

CPC classification number: H03K17/223 ,  G01R31/2832 ,  G06F1/24 ,  G06F1/30 ,  H03K5/19 ,  H03K17/22 ,  H03K19/20

Abstract: A power management circuit includes both a power on reset (POR) circuit and a voltage monitoring circuit. Explicit testing of these circuits is accomplished by controlling voltages applied to the circuits and monitoring an output signal responsive to a logical combination of outputs from the POR circuit and voltage monitoring circuit. The applied voltages are controlled with respect to timing of application, fixing of voltages and varying of voltages in a manner where a certain one of the circuits for explicit test is isolated with change in logic state of the output signal being indicative of operation of that isolated circuit.

公开(公告)号：US12272416B2

公开(公告)日：2025-04-08

申请号：US18661914

申请日：2024-05-13

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan Srinivasan ,  Balwinder Singh Soni ,  Avneep Kumar Goyal

IPC: G11C29/00 ,  G11C7/10 ,  G11C7/22 ,  G11C29/14 ,  G11C29/36 ,  G11C29/38 ,  G11C29/12 ,  H03K19/20

Abstract: A system includes a write-data register and a read-data register, each clocked by a clock signal, and a first-in-first-out (FIFO) buffer coupled between the write-data register and the read-data register, the FIFO buffer including latches configured to store data. The system further includes glue logic with first, second, and third logic circuits configured to generate an internal write enable signal, an internal read valid signal, and an internal read enable signal based on an operational mode of the system. The system is configured to be selectively switched between a normal operational mode, where the latches are accessed for reading and writing by a read enable signal and write enable signal based on a read address signal and a write address signal, and a transition testing mode, where the latches are tested using the internal write enable signal, the internal read enable signal, and the internal read valid signal.

公开(公告)号：US20240426907A1

公开(公告)日：2024-12-26

申请号：US18338082

申请日：2023-06-20

Applicant: STMicroelectronics International N.V.

Inventor： Shiv Kumar Vats ,  Umesh Chandra Srivastava ,  Venkata Narayanan Srinivasan

IPC: G01R31/3185

Abstract: An integrated circuit includes a first set and a second set of scan flip flops, a circuit under test, and a controller. Each scan flip flop of the first set includes a scan enable input coupled to a first scan enable signal. The circuit under test includes logic elements downstream of the first set. The second set includes at least one scan flip flop downstream of the logic elements. Each scan flip flop of the second set includes a scan enable input coupled to a second scan enable signal. The controller is configured to test the logic elements by shifting test patterns into the first set while asserting both the first and second scan enable signal, launching the test patterns, and capturing results from the second set while continuing to assert the first scan enable signal and deasserting the second scan enable signal.