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公开(公告)号：US12019118B2
公开(公告)日：2024-06-25
申请号：US18186549
申请日：2023-03-20
Inventor： Roberto Colombo , Vivek Mohan Sharma , Samiksha Agarwal
IPC: G01R31/317
CPC classification number: G01R31/31703 , G01R31/31722
Abstract: In an embodiment a processing system includes a test circuit configured to set an address value, an upper address limit and a lower address limit to a given reference bit sequence, verify whether the upper-limit comparison signal has a respective third logic level and/or whether the lower-limit comparison signal has the respective third logic level, assert an error signal in response to determining that the upper-limit comparison signal does not have the respective third logic level or the lower-limit comparison signal does not have the respective third logic level, repeat a certain operation for each of the N bits.
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公开(公告)号：US20230314506A1
公开(公告)日：2023-10-05
申请号：US18186624
申请日：2023-03-20
Inventor： Roberto Colombo , Vivek Mohan Sharma
IPC: G01R31/317 , G01R31/3185
CPC classification number: G01R31/31721 , G01R31/31724 , G01R31/318566
Abstract: In an embodiment a processing system includes a reset circuit configured to receive a reset-request signal and one or more further reset-request signals, wherein the one or more further reset-request signals are provided by a processing core, one or more further circuits and/or a terminal of the processing system and to generate a combined reset-request signal by combining the reset-request signal and the one or more further reset-request signals, and a hardware test circuit including for each of the one or more further reset-request signals, a respective first combinational circuit configured to selectively assert the respective further reset-request signal, a second combinational logic circuit configured to selectively mask the combined reset-request signal, and a control circuit configured to repeat operations during a diagnostic phase.
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