Abstract:
A display device includes a display panel including pixels in one pixel column and a gate driver for sequentially providing scan signals to the pixels. Each of the pixels includes a light emitting element, a first transistor for controlling a current amount of driving current flowing through the light emitting element and a second transistor for transferring a data signal to a gate electrode of the first transistor in response to a corresponding scan signal among the scan signals. A first pixel among the pixels is electrically connected to a first data line, and a second pixel adjacent to the first pixel among the pixels is electrically connected to a second data line different from the first data line. A second scan signal provided to the second pixel partially overlaps with a first scan signal provided to the first pixel.
Abstract:
A display device includes a display panel including pixels in one pixel column and a gate driver for sequentially providing scan signals to the pixels. Each of the pixels includes a light emitting element, a first transistor for controlling a current amount of driving current flowing through the light emitting element and a second transistor for transferring a data signal to a gate electrode of the first transistor in response to a corresponding scan signal among the scan signals. A first pixel among the pixels is electrically connected to a first data line, and a second pixel adjacent to the first pixel among the pixels is electrically connected to a second data line different from the first data line. A second scan signal provided to the second pixel partially overlaps with a first scan signal provided to the first pixel.
Abstract:
A stage including a node control unit which controls a voltage of a first control node and a voltage of a second control node, in correspondence with a first input signal supplied to a first input terminal, a second input signal supplied to a second input terminal, and a third input signal supplied to a third input terminal, a node maintenance unit which maintains the voltage of the first control node to be constant in correspondence with the voltage of the second control node, and an output unit which supplies a first gate voltage supplied to a first power terminal or a second gate voltage supplied to a second power terminal to an output terminal in correspondence with the voltage of the first control node and the voltage of the second control node.
Abstract:
An organic light emitting diode (OLED) display includes: a display area comprising a plurality of pixel rows configured to emit light in response to a light emission signal; a light emission signal generator at the periphery of the display area, and including a plurality of light emission signal stages connected to the plurality of pixel rows; and a first high voltage transmission line and a second high voltage transmission line connected to the light emission signal generator, wherein the first high voltage transmission line is connected to a plurality of odd-numbered light emission signal stages among the plurality of light emission signal stages, and the second high voltage transmission line is connected to a plurality of even-numbered light emission signal stages among the plurality of light emission signal stages.
Abstract:
A display device includes: a first pixel region including first pixels, each of the first pixels including a driving transistor to be initialized by a first initialization power source supplied from a first power line; a second pixel region including second pixels, each of the second pixels including a driving transistor to be initialized by a second initialization power source supplied from a second power line; and a power supplier to supply the first initialization power source and the second initialization power source, the first initialization power source and the second initialization power source having a same voltage level when the display device is driven in a first mode, and the first initialization power source and the second initialization power source having different voltage levels during at least one frame period when the display device is driven in a second mode.
Abstract:
A driver includes a first stage, a second stage, and a third stage. The first stage includes a first input terminal and a second input terminal. The first input terminal is electrically connected to a first clock line, which may transmit a first clock signal. The second input terminal is electrically connected to a second clock line, which may transmit a second clock signal. The second stage includes a third input terminal and a fourth input terminal. The third input terminal is electrically connected through the second input terminal to the second clock line. The fourth input terminal is electrically connected to the first clock line. The third stage includes a fifth input terminal and a sixth input terminal. The fifth input terminal is electrically connected through the fourth input terminal to the first clock line. The sixth input terminal is electrically connected to the second clock line.
Abstract:
A display device includes: a light emitting element on a substrate; a first transistor configured to control a driving current flowing in the light emitting element; a second transistor configured to supply a data voltage to the gate electrode of the first transistor based on a first gate signal; a third transistor configured to supply a first reference voltage to the gate electrode of the first transistor based on a second gate signal; a fourth transistor configured to supply a second reference voltage different from the first reference voltage to the drain electrode of the first transistor based on a third gate signal; a fifth transistor configured to supply a driving voltage to the drain electrode of the first transistor based on a first emission signal; and a hold capacitor connected between a second reference line supplying the second reference voltage and the source electrode of the first transistor.
Abstract:
A display device may include a pixel that includes a first transistor, a second transistor including a gate electrode coupled to a first scan line, and first and second electrodes, a third transistor including a gate electrode coupled to a second scan line, and first and second electrodes, a fourth transistor including a gate electrode coupled to a third scan line, and first and second electrodes, a fifth transistor including a gate electrode coupled to a fourth scan line, and first and second electrodes, a sixth transistor including a gate electrode coupled to a fifth scan line, and first and second electrodes, and a first capacitor. The display device may be, during a first period of a frame period, to concurrently apply a turn-on level scan signal to the third scan line, and apply turn-off level scan signals to the first, second, fourth and fifth scan lines.
Abstract:
Provided are a display device. The display device comprises: a display unit defined by a display area and a non-display area located outside the display area, and including pixels arranged in the display area, first sensing wirings electrically connected to the pixels, and auxiliary voltage wirings electrically separated from the pixels; and a sensing unit electrically connected to the first sensing wirings, wherein the first sensing wirings and the auxiliary voltage wirings extend in a first direction and are sequentially arranged along a second direction perpendicular to the first direction at first intervals, the first sensing wirings are spaced apart from each other along the second direction at second intervals greater than the first intervals and are electrically separated from each other, and the auxiliary voltage wirings are electrically connected to each other.
Abstract:
A display device includes a pixel unit including first pixels in a first pixel area, second pixels in a second pixel area, and third pixels in a third pixel area; a first scan driver including first multiplexers configured to operate in response to a first mode and a second mode different from the first mode, and to supply first scan signals to first scan lines connected to the first pixels; a second scan driver configured to supply second scan signals to second scan lines connected to the second pixels; and a third scan driver including second multiplexers configured to operate in response to the first mode and the second mode, and to supply third scan signals to third scan lines connected to the third pixels.