公开(公告)号：US20140241098A1

公开(公告)日：2014-08-28

申请号：US14069188

申请日：2013-10-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Pil SON ,  Young-Soo SOHN ,  Chul-Woo PARK ,  Cheol-Heui PARK

IPC: G11C8/06

CPC classification number: G11C8/06 ,  G11C7/12 ,  G11C8/10 ,  G11C16/24 ,  G11C29/18 ,  G11C2029/1204 ,  G11C2029/1806

Abstract: A memory device may be provided which includes a memory cell array including a plurality of sub arrays each sub array having a plurality of memory cells connected to bit lines; an address buffer configured to receive a row address and a column address; and a column decoder configured to receive the column address from the address buffer and, for each of the sub arrays, to select a column selection line corresponding to the column address, from among a plurality of column selection lines, based on different offset values applied to the sub arrays, respectively. The selected column selection lines correspond to bit lines having different physical locations, respectively, according to the different offset values.

Abstract translation: 可以提供一种存储器件，其包括包括多个子阵列的存储单元阵列，每个子阵列具有连接到位线的多个存储器单元; 配置为接收行地址和列地址的地址缓冲器; 以及列解码器，被配置为从地址缓冲器接收列地址，并且对于每个子阵列，基于应用的不同偏移值从多个列选择线中选择与列地址相对应的列选择线 分别到子阵列。 所选择的列选择线分别对应于具有不同物理位置的位线，根据不同的偏移值。

公开(公告)号：US20140112086A1

公开(公告)日：2014-04-24

申请号：US14057556

申请日：2013-10-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chul-Woo PARK ,  Joo-Sun CHOI ,  Hong-Sun HWANG

IPC: G11C11/406

CPC classification number: G11C11/40618 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/408 ,  G11C29/023 ,  G11C29/028 ,  G11C2211/4065

Abstract: A refresh method for a volatile memory device includes refreshing memory cells of a first set of rows of an array at a first refresh rate having a first refresh period, the first refresh rate being a lower rate having a longer refresh period than a second refresh rate having a second refresh period, wherein each memory cell in the first set of rows of the array has a retention time longer than the first refresh period; and refreshing memory cells of a second set of rows of the array at a third refresh rate having a third refresh period, the third refresh rate being a higher rate having a shorter refresh period than the second refresh rate having the second refresh period, wherein at least one memory cell of each row of the second set of rows has a retention time longer than the third refresh period and shorter than the first refresh period. The second refresh period corresponds to a refresh period defined in a standard for the volatile memory device.

Abstract translation: 用于易失性存储器件的刷新方法包括以具有第一刷新周期的第一刷新率来刷新阵列的第一组行的存储器单元，第一刷新率是具有比第二刷新率更长的刷新周期的较低速率 具有第二刷新周期，其中所述阵列的所述第一组行中的每个存储器单元具有比所述第一刷新周期更长的保持时间; 以及具有第三刷新周期的第三刷新率的阵列的第二组行的刷新存储单元，所述第三刷新率是具有比具有所述第二刷新周期的所述第二刷新率更短的刷新周期的较高速率，其中， 第二组行的每行的至少一个存储单元具有比第三刷新周期长的保留时间并且比第一刷新周期短。 第二刷新周期对应于在易失性存储器件的标准中定义的刷新周期。

公开(公告)号：US20200044458A1

公开(公告)日：2020-02-06

申请号：US16339132

申请日：2017-09-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Geun YOON ,  Kang-Jun KO ,  Chul-Woo PARK ,  Ku-Chul JUNG ,  Seung-Chul CHOI

IPC: H02J7/00

Abstract: A battery charging method and an electronic device are disclosed. The electronic device can comprise: a connection unit comprising a first terminal to which a voltage is applied by an external device, and a second terminal for transmitting/receiving data; a first charging unit for charging a battery connected to the electronic device by using the voltage applied to the first terminal; and a second charging unit for charging the battery by dropping the voltage applied to the first terminal according to a preset voltage drop rate. The first charging unit can comprise: a first switch connected to the first terminal; a communication unit for transmitting information through the second terminal; and a first control unit for acquiring first information on the battery voltage, controlling the communication unit such that the first information is transmitted to a charger connected to the connection unit, and controlling the first switch such that the voltage adjusted on the basis of the first information by the charger is supplied to the second charging unit through the first terminal.

公开(公告)号：US20180262027A1

公开(公告)日：2018-09-13

申请号：US15916653

申请日：2018-03-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ku-Chul JUNG ,  Chul-Woo PARK ,  Sang-Hyun RYU ,  Min-Jung PARK ,  Jeong-Ho LEE ,  Chi-Hyun CHO

IPC: H02J7/00 ,  G01R31/02 ,  G01R31/36 ,  H01M10/0525

Abstract: Various embodiments relating to an electronic device and a method based on a battery leakage state have been described. According to an example embodiment, an electronic device includes a display; a communication circuit; a battery; a current sensor configured to measure a charge current used for charging the battery; and a processor, wherein the processor may be configured to measure a charge current using the current sensor, to determine a leakage state of the battery based on at least a part of the charge current, and to provide a notification corresponding to the leakage state through the display and/or perform a specified function corresponding to the leakage state based on at least a part of the leakage state.

公开(公告)号：US20160351244A1

公开(公告)日：2016-12-01

申请号：US15236895

申请日：2016-08-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Soo SOHN ,  Chul-Woo PARK ,  Si-Hong KIM ,  KWANG-IL PARK ,  Jae-Youn YOUN

IPC: G11C11/406 ,  G11C11/408 ,  G11C11/4076

CPC classification number: G11C11/406 ,  G11C11/4076 ,  G11C11/4087

Abstract: A memory device includes a memory cell array, an intensively accessed row detection circuit, and a refresh control circuit. The memory cell array includes a plurality of memory cell rows. The intensively accessed row detection circuit generates an intensively accessed row address indicating an intensively accessed memory cell row among the plurality of memory cell rows based on an accumulated access time for each of the plurality of memory cell rows. The refresh control unit preferentially refreshes neighboring memory cell rows adjacent to the intensively accessed memory cell row indicated by the intensively accessed row address when receiving the intensively accessed row address from the intensively accessed row detection unit. The memory device effectively reduces a rate of data loss.

公开(公告)号：US20160156203A1

公开(公告)日：2016-06-02

申请号：US14952002

申请日：2015-11-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yun-Hui HAN ,  Chul-Woo PARK ,  Kisun LEE

IPC: H02J7/00 ,  H02J7/35

CPC classification number: H02J7/007 ,  H02J7/0055 ,  H02J7/35

Abstract: A method of performing a charging function by using different types of energy sources and an electronic device thereof are provided. The electronic device includes different types of circuits configured to acquire different types of energy sources, and a processor configured to determine an energy source for charging among the different types of energy sources based on respective current values for the different types of energy sources, and control the determined energy source for charging so as to be used in battery charging of the electronic device or in a system operation of the electronic device.

Abstract translation: 提供了通过使用不同类型的能量来执行充电功能的方法及其电子装置。 电子设备包括被配置为获取不同类型的能量源的不同类型的电路，以及被配置为基于用于不同类型的能源的各自的电流值来确定用于在不同类型的能量源之间进行充电的能量源的处理器，以及控制 所确定的充电能量源用于电子设备的电池充电或电子设备的系统操作。

公开(公告)号：US20150134895A1

公开(公告)日：2015-05-14

申请号：US14465995

申请日：2014-08-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Soo SOHN ,  Chul-Woo PARK ,  Kwang-Il PARK ,  Hak-Soo YU

IPC: G11C14/00 ,  G11C11/00

CPC classification number: G11C14/0018 ,  G11C11/40 ,  G11C29/702 ,  G11C29/785 ,  G11C2029/4402

Abstract: A semiconductor memory device may include a cell array comprising a plurality of memory cells, each memory cell connected to a word line and a bit line, the cell array divided into a plurality of blocks, each block including a plurality of word lines, the plurality of blocks including at least a first defective block; a nonvolatile storage circuit configured to store address information of the first defective block, and to output the address information to an external device; and a fuse circuit configured to cut off an activation of word lines of the first defective block.

Abstract translation: 半导体存储器件可以包括包括多个存储器单元的单元阵列，每个存储器单元连接到字线和位线，单元阵列被划分成多个块，每个块包括多个字线，多个字线 的至少包括第一缺陷块的块; 非易失性存储电路，被配置为存储所述第一缺陷块的地址信息，并将所述地址信息输出到外部设备; 以及熔丝电路，被配置为切断第一有缺陷块的字线的激活。

公开(公告)号：US20150003141A1

公开(公告)日：2015-01-01

申请号：US14220275

申请日：2014-03-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Pil SON ,  Chul-Woo PARK ,  Young-Soo SOHN

IPC: G11C29/00 ,  G11C11/407 ,  G11C17/16

CPC classification number: G11C29/846 ,  G11C17/16 ,  G11C29/785

Abstract: A semiconductor memory device is provided which includes a memory cell group and a fuse cell group including at least one fuse cell to store a failed address corresponding to a defective memory cell in the memory cell group; a spare cell group including a spare memory cell configured to replace the defective memory cell included in the memory cell group; a data sensing/selection circuit configured to read data stored in the memory cell group and the spare cell group in response to an activation of the word line; a fuse sense amplifier configured to read the failed address in response to the activation of the word line; and a repair logic circuit configured to control the data sensing/selection circuit in response to the failed address such that the defective memory cell in the memory cell group is replaced by the spare memory cell.

Abstract translation: 提供了一种半导体存储器件，其包括存储单元组和熔丝单元组，所述熔丝单元组包括至少一个熔丝单元，用于存储与所述存储单元组中的有缺陷存储单元相对应的故障地址; 备用单元组，其包括被配置为替换所述存储单元组中包括的所述有缺陷的存储单元的备用存储单元; 数据感测/选择电路，被配置为响应于字线的激活读取存储在存储单元组和备用单元组中的数据; 熔丝读出放大器，被配置为响应于字线的激活读取失败的地址; 以及修复逻辑电路，被配置为响应于所述故障地址来控制所述数据检测/选择电路，使得所述存储单元组中的所述有缺陷的存储器单元被所述备用存储单元替换。

公开(公告)号：US20140149652A1

公开(公告)日：2014-05-29

申请号：US14090510

申请日：2013-11-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chul-Woo PARK ,  Dong-Soo KANG ,  Su-A KIM ,  Jun-hee YOO ,  Hak-Soo YU ,  Jae-Youn YOUN ,  Sung-hyun LEE ,  Kyoung-Heon JEONG ,  Hyo-Jin CHOI ,  Young-Soo SOHN

IPC: G11C7/10

CPC classification number: G11C7/1072 ,  G06F12/0223 ,  G06F12/0292 ,  G11C29/76 ,  G11C29/84

Abstract: In one example embodiment, a memory system includes a memory module and a memory controller. The memory module is configured generate density information of the memory module based on a number of the bad pages of the memory module, the bad pages being pages that have a fault. The memory controller is configured to map a continuous physical address to a dynamic random access memory (dram) address of the memory module based on the density information received from the memory module.

Abstract translation: 在一个示例性实施例中，存储器系统包括存储器模块和存储器控制器。 配置存储器模块基于存储器模块的不良页面的数量生成存储器模块的密度信息，坏页面是具有故障的页面。 存储器控制器被配置为基于从存储器模块接收的密度信息将连续的物理地址映射到存储器模块的动态随机存取存储器（显存）地址。

公开(公告)号：US20140146624A1

公开(公告)日：2014-05-29

申请号：US14087167

申请日：2013-11-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Pil SON ,  Uk-Song KANG ,  Chul-Woo PARK ,  Young-Soo SOHN

IPC: G11C29/00

CPC classification number: G11C29/4401 ,  G06F11/1048 ,  G11C5/04 ,  G11C29/808 ,  G11C2029/0409 ,  G11C2029/0411

Abstract: In one example embodiment, a memory module includes a plurality of memory devices and a buffer chip configured to manage the plurality of memory device. The buffer chip includes a memory management unit having an error correction unit configured to perform error correction operation on each of the plurality of memory devices. Each of the plurality of memory devices includes at least one spare column that is accessible by the memory management unit, and the memory management unit is configured to correct errors of the plurality of memory devices by selectively using the at least one spare column based on an error correction capability of the error correction unit.

Abstract translation: 在一个示例实施例中，存储器模块包括多个存储器件和被配置为管理多个存储器件的缓冲器芯片。 缓冲器芯片包括具有错误校正单元的存储器管理单元，该单元被配置为对多个存储器件中的每一个进行纠错操作。 多个存储器设备中的每一个包括至少一个可由存储器管理单元访问的备用列，并且存储器管理单元被配置为通过有选择地使用至少一个备用列来校正多个存储器件的错误， 纠错单元的纠错能力。