公开(公告)号：US10431593B2

公开(公告)日：2019-10-01

申请号：US15860082

申请日：2018-01-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jang-Gn Yun ,  Sung-Min Hwang ,  Joon-Sung Lim ,  Kyoil Koo ,  Hoosung Cho ,  Sunyoung Kim ,  Cheol Ryou ,  Jaesun Yun

IPC: H01L27/11582 ,  H01L29/10 ,  H01L29/423 ,  H01L27/11565 ,  H01L27/1157

Abstract: Disclosed is a three-dimensional semiconductor memory device that includes first to third channel groups arranged in a first direction on a substrate. The first to third channel groups are spaced apart from each other along a second direction on the substrate. Each of the first to third channel groups includes a plurality of vertical channels that extend in a third direction perpendicular to a top surface of the substrate. The first and second channel groups are adjacent to each other in the second direction and spaced apart at a first distance in the second direction. The second and third channel groups are adjacent to each other in the second direction and are spaced apart at a second distance that is less than the first distance.

公开(公告)号：US20170148748A1

公开(公告)日：2017-05-25

申请号：US15352890

申请日：2016-11-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeho JEONG ,  Sunyoung Kim ,  Jang-Gn Yun ,  Hoosung Cho ,  Sunghoi Hur

IPC: H01L23/00 ,  H01L23/544 ,  H01L23/528 ,  H01L27/115 ,  H01L23/522

Abstract: Three-dimensional (3D) semiconductor devices may be provided. A 3D semiconductor device may include a substrate including a chip region and a scribe line region, a cell array structure including memory cells three-dimensionally arranged on the chip region of the substrate, a stack structure disposed on the scribe line region of the substrate and including first layers and second layers that are vertically and alternately stacked, and a plurality of vertical structures extending along a vertical direction that is perpendicular to a top surface of the substrate and penetrating the stack structure.

公开(公告)号：US11871571B2

公开(公告)日：2024-01-09

申请号：US17517137

申请日：2021-11-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soodoo Chae ,  Myoungbum Lee ,  HuiChang Moon ,  Hansoo Kim ,  JinGyun Kim ,  Kihyun Kim ,  Siyoung Choi ,  Hoosung Cho

IPC: H10B43/27 ,  H10B43/10 ,  H10B43/20 ,  H10B43/50 ,  H01L23/498 ,  H01L23/535 ,  H01L29/40 ,  H01L29/423 ,  H01L23/522

CPC classification number: H10B43/27 ,  H01L23/49844 ,  H01L23/5226 ,  H01L23/535 ,  H01L29/408 ,  H01L29/4234 ,  H10B43/10 ,  H10B43/20 ,  H10B43/50 ,  H01L2924/0002 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes.

公开(公告)号：US11456335B2

公开(公告)日：2022-09-27

申请号：US17031037

申请日：2020-09-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongho Lim ,  Hoosung Cho ,  Hongsoo Kim

IPC: H01L27/24 ,  H01L27/115 ,  H01L21/768 ,  H01L23/522 ,  H01L27/11582 ,  H01L27/11573 ,  H01L27/11568 ,  H01L27/112 ,  H01L23/48

Abstract: A vertical memory device includes circuit patterns of peripheral circuits on a substrate, the circuit patterns including a lower conductive pattern, cell stack structures over the circuit patterns and spaced apart in a first horizontal direction, wherein each of the cell stack structures includes gate electrodes spaced apart in a vertical direction, a first insulating interlayer covering the cell stack structures and a portion between the cell stack structures, a through via contact passing through the first insulating interlayer between the cell stack structures to contact an upper surface of the lower conductive pattern, at least one dummy through via contact passing through the first insulating interlayer between the cell stack structures and disposed adjacent to the through via contact, and upper wiring on the through via contact.

公开(公告)号：US11387249B2

公开(公告)日：2022-07-12

申请号：US16708482

申请日：2019-12-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soodoo Chae ,  Myoungbum Lee ,  HuiChang Moon ,  Hansoo Kim ,  JinGyun Kim ,  Kihyun Kim ,  Siyoung Choi ,  Hoosung Cho

IPC: H01L27/11582 ,  H01L27/11578 ,  H01L27/11575 ,  H01L23/498 ,  H01L23/535 ,  H01L29/40 ,  H01L29/423 ,  H01L23/522 ,  H01L27/11565

Abstract: A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes.