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    Display apparatus and control method thereof
    13.
    发明授权
    Display apparatus and control method thereof 有权

    公开(公告)号：US12020626B2

    公开(公告)日：2024-06-25

    申请号：US18139769

    申请日：2023-04-26

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sungjin Lim ,  Minhong Park ,  Jihye Kim ,  Kyeongjin Lee ,  Dongki Lee ,  Youngho Jung

    IPC: G09G3/20

    CPC classification number: G09G3/2092 ,  G09G2310/0245 ,  G09G2310/0267 ,  G09G2310/0275 ,  G09G2354/00

    Abstract: A display apparatus includes a panel driver; a display panel including a plurality of pixels connected to a plurality of gate lines and a plurality of data lines through a plurality of switching elements; and a processor configured to control the panel driver to output a gate signal through the plurality of gate lines, and display an image in the display panel by controlling the panel driver to apply, through the plurality of data lines, data voltage to pixels, from among the plurality of pixels, connected with switching elements, from among the plurality of switching elements, to which the gate signal is output, wherein the processor is further configured to control, based on a user input for selecting a ratio of the image, the panel driver to output the gate signal to at least one first gate line connected with a first subset of pixels, from among the plurality of pixels, for displaying the image according to the user input.

    Memory device transmitting and receiving data at high speed and low power
    19.
    发明授权
    Memory device transmitting and receiving data at high speed and low power 有权

    公开(公告)号：US11295808B2

    公开(公告)日：2022-04-05

    申请号：US17084345

    申请日：2020-10-29

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Byongmo Moon ,  Jihye Kim ,  Je Min Ryu ,  Beomyong Kil ,  Sungoh Ahn

    IPC: G11C11/4076 ,  G11C11/4093 ,  G06F3/06 ,  G11C11/4096 ,  H01L25/18

    Abstract: A memory device includes a control logic circuit, a write data strobe signal divider, a data transceiver, and a memory cell array. The control logic circuit generates a reset signal before a write data strobe signal provided from a memory controller starts to toggle. The write data strobe signal divider generates internal write data strobe signals that toggle depending on toggling of the write data strobe signal, the internal write data strobe signals toggling with different phases, respectively. The control logic circuit initializes the internal write data strobe signals to given values in response to the reset signal. The data transceiver receives write data provided from the memory controller based on the internal write data strobe signals. The memory cell array stores the received write data.

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