公开(公告)号：US20230402456A1

公开(公告)日：2023-12-14

申请号：US18165486

申请日：2023-02-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoo Ri SUNG ,  Ju Youn KIM ,  Myung Soo SEO ,  Ki Hwan LEE

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/092 ,  H01L21/823807 ,  H01L21/823864

Abstract: A semiconductor device includes a substrate that includes a first region and a second region, a first active pattern on the first region and that extends in a first horizontal direction, a second active pattern on the second region and that extends in the first horizontal direction, a first etch stop layer on the first active pattern, a second etch stop layer on the second active pattern, a plurality of first nanosheets on the first etch stop layer and that are stacked in a vertical direction and include silicon germanium (SiGe), a plurality of second nanosheets on the second etch stop layer and that are stacked in the vertical direction, a first gate electrode on the first etch stop layer and that extends in a second horizontal direction, and a second gate electrode disposed on the second etch stop layer and that extends in the second horizontal direction.

公开(公告)号：US20230378174A1

公开(公告)日：2023-11-23

申请号：US18230052

申请日：2023-08-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Min YOO ,  Ju Youn KIM ,  Hyung Joo NA ,  Bong Seok SUH ,  Joo Ho JUNG ,  Eui Chul HWANG ,  Sung Moon LEE

IPC: H01L27/088 ,  H01L29/40 ,  H01L21/762 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L29/408 ,  H01L21/76224 ,  H01L29/7846

Abstract: A semiconductor device includes a first active pattern extending lengthwise along a first direction and a second active pattern extending lengthwise along the first direction and spaced apart from the first active pattern in the first direction. The device also includes a field insulating film between the first active pattern and the second active pattern. An upper surface of the field insulating film is lower than or coplanar with upper surfaces of the first and second active patterns. The device further includes an element isolation structure in an isolation trench in the first active pattern and the field insulating film. An upper surface of the element isolation structure is higher than the upper surfaces of the first and second active patterns.

公开(公告)号：US20210366905A1

公开(公告)日：2021-11-25

申请号：US17393025

申请日：2021-08-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Min YOO ,  Ju Youn KIM ,  Hyung Joo NA ,  Bong Seok SUH ,  Joo Ho JUNG ,  Eui Chul HWANG ,  Sung Moon LEE

IPC: H01L27/088 ,  H01L29/40 ,  H01L21/762 ,  H01L29/78

Abstract: A semiconductor device includes a first active pattern extending lengthwise along a first direction and a second active pattern extending lengthwise along the first direction and spaced apart from the first active pattern in the first direction. The device also includes a field insulating film between the first active pattern and the second active pattern. An upper surface of the field insulating film is lower than or coplanar with upper surfaces of the first and second active patterns. The device further includes an element isolation structure in an isolation trench in the first active pattern and the field insulating film. An upper surface of the element isolation structure is higher than the upper surfaces of the first and second active patterns.

公开(公告)号：US20210257474A1

公开(公告)日：2021-08-19

申请号：US17039083

申请日：2020-09-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： In Yeal LEE ,  Ju Youn KIM ,  Jin-Wook KIM ,  Ju Hun PARK ,  Deok Han BAE ,  Myung Yoon UM

IPC: H01L29/423 ,  H01L23/522 ,  H01L23/528 ,  H01L29/49

Abstract: A semiconductor device includes a substrate, a gate structure on the substrate, and a gate contact in the gate structure. The gate structure includes a gate electrode extending in a first direction and a gate capping pattern on the gate electrode. The gate contact is connected to the gate electrode. The gate electrode includes a protrusion extending along a boundary between the gate contact and the gate capping pattern.

公开(公告)号：US20210005603A1

公开(公告)日：2021-01-07

申请号：US17025497

申请日：2020-09-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Min YOO ,  Ju Youn KIM ,  Hyung Joo NA ,  Bong Seok SUH ,  Joo Ho JUNG ,  Eui Chul HWANG ,  Sung Moon LEE

IPC: H01L27/088 ,  H01L29/40 ,  H01L21/762 ,  H01L29/78

Abstract: A semiconductor device includes a first active pattern extending lengthwise along a first direction and a second active pattern extending lengthwise along the first direction and spaced apart from the first active pattern in the first direction. The device also includes a field insulating film between the first active pattern and the second active pattern. An upper surface of the field insulating film is lower than or coplanar with upper surfaces of the first and second active patterns. The device further includes an element isolation structure in an isolation trench in the first active pattern and the field insulating film. An upper surface of the element isolation structure is higher than the upper surfaces of the first and second active patterns.

公开(公告)号：US20200043929A1

公开(公告)日：2020-02-06

申请号：US16368990

申请日：2019-03-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eui Chul HWANG ,  Ju Youn KIM ,  Hyung Joo NA ,  Bong Seok SUH ,  Sang Min YOO ,  Joo Ho JUNG ,  Sung Moon LEE

IPC: H01L27/092 ,  H01L27/02 ,  H01L29/423 ,  H01L29/08 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/311 ,  H01L21/306 ,  H01L21/762

Abstract: A semiconductor device and a method for fabricating the same, the device including an active pattern extending in a first direction on a substrate; a field insulating film surrounding a part of the active pattern; a first gate structure extending in a second direction on the active pattern and the field insulating film, a second gate structure spaced apart from the first gate structure and extending in the second direction on the active pattern and the field insulating film; and a first device isolation film between the first and second gate structure, wherein a side wall of the first gate structure facing the first device isolation film includes an inclined surface having an acute angle with respect to an upper surface of the active pattern, and a lowermost surface of the first device isolation film is lower than or substantially coplanar with an uppermost surface of the field insulating film.

公开(公告)号：US20170213826A1

公开(公告)日：2017-07-27

申请号：US15413680

申请日：2017-01-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju Youn KIM ,  Gi Gwan PARK

IPC: H01L27/088 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/11 ,  H01L29/49 ,  H01L29/423

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823456 ,  H01L27/088 ,  H01L27/1104 ,  H01L28/00 ,  H01L29/42372 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/7854

Abstract: A semiconductor device including a substrate includes a first region and a second region and first and second transistors in the first and second regions, respectively. The first transistor includes a first gate insulating layer on the substrate, a first lower TiN layer on and in contact with the first gate insulating layer, a first etch-stop layer on the first lower TiN layer and a first upper gate electrode on the first etch-stop layer. The second transistor includes a second gate insulating layer on the substrate, a second lower TiN layer on and in contact with the second gate insulating layer, a second etch-stop layer on the second lower TiN layer and a second upper gate electrode on the second etch-stop layer. A thickness of the first lower TiN layer is less than a thickness of the second lower TiN layer

公开(公告)号：US20250126882A1

公开(公告)日：2025-04-17

申请号：US18991796

申请日：2024-12-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Min YOO ,  Ju Youn KIM ,  Hyung Joo NA ,  Bong Seok SUH ,  Joo Ho JUNG ,  Eui Chul HWANG ,  Sung Moon LEE

IPC: H10D84/83 ,  H01L21/762 ,  H10D30/69 ,  H10D64/00

Abstract: A semiconductor device includes a first active pattern extending lengthwise along a first direction and a second active pattern extending lengthwise along the first direction and spaced apart from the first active pattern in the first direction. The device also includes a field insulating film between the first active pattern and the second active pattern. An upper surface of the field insulating film is lower than or coplanar with upper surfaces of the first and second active patterns. The device further includes an element isolation structure in an isolation trench in the first active pattern and the field insulating film. An upper surface of the element isolation structure is higher than the upper surfaces of the first and second active patterns.

公开(公告)号：US20240332090A1

公开(公告)日：2024-10-03

申请号：US18388348

申请日：2023-11-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju Youn KIM ,  Myung Soo SEO ,  Joong Gun OH ,  Seul Gi YUN ,  Jin Woo KIM

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L21/823807 ,  H01L21/82385 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545

Abstract: A method for fabricating a semiconductor device includes providing a substrate having first to fourth regions defined thereon. First to fourth active patterns are formed in the first to fourth regions, respectively. Each of the first to fourth active patterns extends in a first horizontal direction. A gate insulating layer is formed on each of the first to fourth active patterns. A first gate electrode is formed in the first region and includes first and fifth layers, a second gate electrode is formed in the second region and includes first, second and fifth layers, a third gate electrode is formed in the third region and includes first, third, fourth and fifth layers and a fourth gate electrode is formed in the fourth region and includes first, second, third, fourth and fifth layers.

公开(公告)号：US20220130827A1

公开(公告)日：2022-04-28

申请号：US17569950

申请日：2022-01-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju Youn KIM ,  Sang Jung KANG ,  Ji Su KANG ,  Yun Sang SHIN

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/786 ,  H01L29/66 ,  H01L21/762 ,  H01L29/423

Abstract: A semiconductor device includes a substrate including NMOS and PMOS regions; first and second active patterns on the NMOS region; third and fourth active patterns on the PMOS region, the third active pattern being spaced apart from the first active pattern; a first dummy gate structure on the first and third active patterns; a second dummy gate structure on the second and fourth active patterns; a normal gate structure on the third active pattern; a first source/drain pattern on the third active pattern and between the normal gate structure and the first dummy gate structure; and a first element separation structure between the first and second dummy gate structures and separating the third and fourth active patterns, wherein the first dummy gate structure includes a first dummy insulation gate intersecting the third active pattern.