公开(公告)号：US20240203855A1

公开(公告)日：2024-06-20

申请号：US18356721

申请日：2023-07-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaemok JUNG ,  Un-Byoung KANG ,  Dowan KIM ,  Sung Keun PARK ,  Jongho PARK ,  Ju-Il CHOI

IPC: H01L23/498 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48

CPC classification number: H01L23/49827 ,  H01L21/565 ,  H01L21/76811 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/08 ,  H01L24/32 ,  H01L2224/08055 ,  H01L2224/08155 ,  H01L2224/32146 ,  H01L2224/32235 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/182

Abstract: An embodiment provides a semiconductor package including: a first redistribution layer substrate; a semiconductor chip on the first redistribution layer substrate; a coupling member on the first redistribution layer substrate, wherein the coupling member is spaced apart from the semiconductor chip; an encapsulant on the first redistribution layer substrate, the semiconductor chip, and the coupling member; and a second redistribution layer substrate on the encapsulant, wherein the coupling member includes a vertical wire and a metal portion extending around the vertical wire, and wherein a first end of the coupling member is electrically connected to the first redistribution layer substrate, and a second end of the coupling member is electrically connected to the second redistribution layer substrate.

公开(公告)号：US20230133977A1

公开(公告)日：2023-05-04

申请号：US17837379

申请日：2022-06-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Se-Ho YOU ,  Ju-Il CHOI

IPC: H01L27/108

Abstract: A semiconductor device including a substrate and first and second packages thereon, the first package includes a first lower redistribution layer; a first core semiconductor stack thereon and including a first core chip and a first through via stacked on the first lower redistribution layer; and a first memory semiconductor stack on the first lower redistribution layer and including first memory chips stacked on the first lower redistribution layer, the second package includes a second lower redistribution layer; a second core semiconductor stack thereon and including a second core chip on the second lower redistribution layer; and a second memory semiconductor stack on the second lower redistribution layer and including second memory chips stacked on the second lower redistribution layer, the first through via penetrates the first core semiconductor stack, and the first and second lower redistribution layers are electrically connected to each other through the first through via.

公开(公告)号：US20220077040A1

公开(公告)日：2022-03-10

申请号：US17318227

申请日：2021-05-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeonggi JIN ,  Gyuho KANG ,  Solji SONG ,  Un-Byoung KANG ,  Ju-Il CHOI

IPC: H01L23/498 ,  H01L23/00

Abstract: A semiconductor package may include a redistribution substrate having a first surface and a second surface, opposite to each other, a semiconductor chip on the first surface of the redistribution substrate, and a solder pattern on the second surface of the redistribution substrate. The redistribution substrate may include an under-bump pattern coupled to the solder pattern, a first redistribution pattern on the under-bump pattern, the first redistribution pattern including a first via portion and a first wire portion, and a first seed pattern between the under-bump pattern and the first redistribution pattern and on a side surface of the first via portion and a bottom surface of the first wire portion. A bottom surface of the first seed pattern may be at a level lower than a top surface of the under-bump pattern.

公开(公告)号：US20210343634A1

公开(公告)日：2021-11-04

申请号：US17099929

申请日：2020-11-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju-Il CHOI ,  Jumyong Park ,  Jin Ho An ,  Chungsun Lee ,  Teahwa Jeong ,  Jeonggi Jin

IPC: H01L23/498 ,  H01L25/10 ,  H01L25/065 ,  H01L23/31

Abstract: An interconnection structure includes a dielectric layer, and a wiring pattern in the dielectric layer. The wiring pattern includes a via body, a first pad body that vertically overlaps the via body, and a line body that extends from the first pad body. The via body, the first pad body, and the line body are integrally connected to each other, and a level of a bottom surface of the first pad body is lower than a level of a bottom surface of the line body.

公开(公告)号：US20250022823A1

公开(公告)日：2025-01-16

申请号：US18904203

申请日：2024-10-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-Il CHOI ,  Pil-Kyu KANG ,  Hoechul KIM ,  Hoonjoo NA ,  Jaehyung PARK ,  Seongmin SON

IPC: H01L23/00 ,  H01L23/31 ,  H01L25/16 ,  H01L27/146

Abstract: A semiconductor device and a semiconductor package, the device including a first buffer dielectric layer on a first dielectric layer; a second dielectric layer and a second buffer dielectric layer sequentially disposed on the first buffer dielectric layer, the second buffer dielectric layer being in contact with the first buffer dielectric layer; and a pad interconnection structure that penetrates the first buffer dielectric layer and the second buffer dielectric layer, wherein the pad interconnection structure includes copper and tin.

公开(公告)号：US20240429189A1

公开(公告)日：2024-12-26

申请号：US18822646

申请日：2024-09-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-Il CHOI ,  Gyuho KANG ,  Heewon KIM ,  Junyoung PARK ,  Seong-Hoon BAE ,  Jin Ho AN

IPC: H01L23/00 ,  H01L23/532 ,  H01L23/538

Abstract: A semiconductor package device may include a redistribution substrate and a semiconductor chip on a top surface of the redistribution substrate. The redistribution substrate may include an under-bump pattern, which includes including a body portion and a protruding portion extended from the body portion to form a single object, an insulating layer covering a side surface of the body portion, and an outer coupling terminal on the protruding portion. The body portion may have a first diameter in a first direction parallel to the top surface of the redistribution substrate, and the protruding portion may have a second diameter in the first direction, which is smaller than the first diameter. A top surface of the protruding portion may be parallel to the first direction, and a side surface of the protruding portion may be inclined at an angle to a top surface of the body portion.

公开(公告)号：US20240312894A1

公开(公告)日：2024-09-19

申请号：US18668974

申请日：2024-05-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-Il CHOI ,  Jumyong PARK ,  Jin Ho AN ,  Dongjoon OH ,  Chungsun LEE ,  Jeonggi JIN ,  Jinho CHUN

IPC: H01L23/498

CPC classification number: H01L23/49838 ,  H01L23/49822

Abstract: A semiconductor package includes a redistribution substrate that includes a first redistribution pattern and a second redistribution pattern that are at different levels from each other, and a semiconductor chip on the redistribution substrate and including a plurality of chip pads electrically connected to the first and second redistribution patterns. The first redistribution pattern includes a first metal pattern on a first dielectric layer, and a first barrier pattern between the first dielectric layer and a bottom surface of the first metal pattern. The second redistribution pattern includes a second metal pattern in a second dielectric layer, and a second barrier pattern between the second dielectric layer and a bottom surface of the second metal pattern and between the second dielectric layer and a sidewall of the second metal pattern.

公开(公告)号：US20220037248A1

公开(公告)日：2022-02-03

申请号：US17364558

申请日：2021-06-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-Il CHOI ,  Jumyong PARK ,  Jin Ho AN ,  Dongjoon OH ,  Chungsun LEE ,  Jeonggi JIN ,  Jinho CHUN

IPC: H01L23/498

Abstract: A semiconductor package includes a redistribution substrate that includes a first redistribution pattern and a second redistribution pattern that are at different levels from each other, and a semiconductor chip on the redistribution substrate and including a plurality of chip pads electrically connected to the first and second redistribution patterns. The first redistribution pattern includes a first metal pattern on a first dielectric layer, and a first barrier pattern between the first dielectric layer and a bottom surface of the first metal pattern. The second redistribution pattern includes a second metal pattern in a second dielectric layer, and a second barrier pattern between the second dielectric layer and a bottom surface of the second metal pattern and between the second dielectric layer and a sidewall of the second metal pattern.