公开(公告)号：US20250126803A1

公开(公告)日：2025-04-17

申请号：US18913098

申请日：2024-10-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seunggeol NAM ,  Sijung YOO ,  Minhyun LEE ,  Hyunjae LEE ,  Seokhoon CHOI

IPC: H10B51/30 ,  H10B51/20

Abstract: A semiconductor device, and a memory apparatus and an electronic apparatus including the same are provided. The semiconductor device may include a gate electrode, a ferroelectric layer on the gate electrode, a channel layer on the ferroelectric layer, and a plurality of nanostructures spaced apart from each other in the ferroelectric layer. The plurality of nanostructures may be adjacent to the gate electrode or the channel layer, or a portion of the plurality of nanostructures may be adjacent to the gate electrode and the rest portion of the plurality of nanostructures may be adjacent to the channel layer.

公开(公告)号：US20250126802A1

公开(公告)日：2025-04-17

申请号：US18761688

申请日：2024-07-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sijung YOO ,  Seunggeol NAM ,  Donghoon KIM ,  Hyunjae LEE ,  Dukhyun CHOE ,  Seokhoon CHOI

IPC: H10B51/30 ,  G06N3/063 ,  H01L29/51 ,  H01L29/78

Abstract: A ferroelectric field effect transistor includes a channel, a gate electrode provided to face the channel, a ferroelectric layer provided between the channel and the gate electrode, an interfacial layer provided between the channel and the ferroelectric layer, and a diffusion barrier layer provided between the ferroelectric layer and the gate electrode, wherein the diffusion barrier layer includes SiON, the diffusion barrier layer has an oxygen concentration gradient that gradually decreases from a first surface of the diffusion barrier layer facing the gate electrode toward a second surface of the diffusion barrier layer facing the ferroelectric layer, and the diffusion barrier layer may have a nitrogen concentration gradient that gradually increases from the first surface toward the second surface.

公开(公告)号：US20240096415A1

公开(公告)日：2024-03-21

申请号：US18335492

申请日：2023-06-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changseok LEE ,  Minhyun LEE ,  Seunggeol NAM

IPC: G11C16/04 ,  H01L29/10 ,  H01L29/18 ,  H01L29/20 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: G11C16/0483 ,  H01L29/1033 ,  H01L29/18 ,  H01L29/2003 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A nonvolatile memory device may include a channel layer extending in a first direction; a plurality of gate electrodes and a plurality of spacers alternately arranged with each other in the first direction, and a gate insulating layer extending in the first direction. Each of the plurality of gate electrodes and each of the plurality of spacers may extend in a second direction crossing the first direction. The gate insulating layer may extend in the first direction. The gate insulating layer may be between the channel layer and the plurality of gate electrodes. The channel layer may include a two-dimensional semiconductor material having an electrically p-type property.

公开(公告)号：US20240015983A1

公开(公告)日：2024-01-11

申请号：US18340560

申请日：2023-06-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinseong HEO ,  Taehwan MOON ,  Seunggeol NAM ,  Hyunjae LEE

IPC: H10B53/20 ,  H10B53/30

CPC classification number: H10B53/20 ,  H10B53/30

Abstract: A three-dimensional (3D) ferroelectric memory device may include a plurality of gate electrodes stacked on a substrate, a plurality of ferroelectric layers in contact with the plurality of gate electrodes, a plurality of intermediate electrodes in contact with the plurality of ferroelectric layers, a gate insulating layer in contact with the plurality of intermediate electrodes, and a channel layer in contact with the gate insulating layer. Widths of the intermediate electrodes may be greater than widths of the ferroelectric layers in contact with the intermediate electrodes.

公开(公告)号：US20240008289A1

公开(公告)日：2024-01-04

申请号：US18340407

申请日：2023-06-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinseong HEO ,  Taehwan MOON ,  Seunggeol NAM ,  Hyunjae LEE

IPC: H10B53/20 ,  H10B53/30

CPC classification number: H10B53/20 ,  H10B53/30

Abstract: Provided is a 3D ferroelectric memory device. The 3D ferroelectric memory device may include a plurality of gate electrodes stacked on a substrate in a first direction; a plurality of ferroelectric layers on the plurality of gate electrodes in a second direction; a plurality of intermediate electrodes on the plurality of ferroelectric layers in the second direction; a first insulating layer between the plurality of gate electrodes and between the plurality of intermediate electrodes; a second insulating layer on the plurality of intermediate electrodes and the first insulating layer; and a channel layer on the second insulating layer.

公开(公告)号：US20230397432A1

公开(公告)日：2023-12-07

申请号：US18329197

申请日：2023-06-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinseong HEO ,  Taehwan MOON ,  Seunggeol NAM ,  Hyunjae LEE ,  Dukhyun CHOE

IPC: H10B53/20 ,  H10B53/10 ,  G11C16/04 ,  H10B51/10 ,  H10B51/20

CPC classification number: H10B53/20 ,  H10B53/10 ,  G11C16/0483 ,  H10B51/10 ,  H10B51/20

Abstract: A memory device includes a plurality of gate electrodes spaced apart from each other in a first direction, a memory layer comprising a plurality of memory regions that protrude and extend in a second direction perpendicular to the first direction to face the plurality of gate electrodes, respectively, a plurality of first insulating layers extended to spaces between the plurality of memory regions between the plurality of gate electrodes, a channel layer disposed between the memory layer and the plurality of gate electrodes, the channel layer having a shape including a plurality of first regions surrounding the plurality of memory regions and a second region that connects the plurality of first regions to each other in the first direction, and a gate insulating layer arranged between the channel layer and the plurality of gate electrodes.

公开(公告)号：US20230093076A1

公开(公告)日：2023-03-23

申请号：US17677654

申请日：2022-02-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hagyoul BAE ,  Seunggeol NAM ,  Jinseong HEO ,  Sanghyun JO ,  Dukhyun CHOE

IPC: H01L29/78 ,  H01L21/66 ,  H01L29/51 ,  H01L29/66

Abstract: Provided are a ferroelectric semiconductor device and a method of extracting a defect density of the same. A ferroelectric electronic device includes a first layer, an insulating layer including a ferroelectric layer and a first interface that is adjacent to the first layer, and an upper electrode over the insulating layer, wherein the insulating layer has a bulk defect density of 1016 cm−3eV−1 or more and an interface defect density of 1010 cm−2eV−1 or more.

公开(公告)号：US20230070266A1

公开(公告)日：2023-03-09

申请号：US17670949

申请日：2022-02-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changhyun KIM ,  Seunggeol NAM ,  Keunwook SHIN ,  Dohyun LEE

IPC: H01L29/45 ,  H01L29/417 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

Abstract: A semiconductor device includes a first source/drain structure including a first semiconductor region and a first electrode in electrical contact with the first semiconductor region; a second source/drain structure including a second semiconductor region and a second electrode in electrical contact with the second semiconductor region; a channel between the first semiconductor region and the second semiconductor region; and a gate structure including a gate insulating film covering the channel and a gate electrode covering the gate insulating film. The first source/drain structure further includes a silicide film between the first semiconductor region and the first electrode and a conductive barrier between the silicide film and the first electrode. The conductive barrier includes a conductive two-dimensional material.

公开(公告)号：US20210327817A1

公开(公告)日：2021-10-21

申请号：US17362308

申请日：2021-06-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunjae SONG ,  Seunggeol NAM ,  Yeonchoo CHO ,  Seongjun PARK ,  Hyeonjin SHIN ,  Jaeho LEE

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522

Abstract: Example embodiments relate to a layer structure having a diffusion barrier layer, and a method of manufacturing the same. The layer structure includes first and second material layers and a diffusion barrier layer therebetween. The diffusion barrier layer includes a nanocrystalline graphene (nc-G) layer. In the layer structure, the diffusion barrier layer may further include a non-graphene metal compound layer or a graphene layer together with the nc-G layer. One of the first and second material layers is an insulating layer, a metal layer, or a semiconductor layer, and the remaining layer may be a metal layer.

公开(公告)号：US20210313439A1

公开(公告)日：2021-10-07

申请号：US17119337

申请日：2020-12-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwanghee LEE ,  Sangwook KIM ,  Seunggeol NAM ,  Taehwan MOON ,  Yunseong LEE ,  Sanghyun JO ,  Jinseong HEO

IPC: H01L29/49 ,  H01L29/786 ,  H01L29/78 ,  H01L29/66 ,  H01L29/40

Abstract: Disclosed herein is an electronic device including: a lower gate electrode; a ferroelectric layer covering the lower gate electrode; a first insertion layer covering the ferroelectric layer and including a dielectric material; a channel layer provided on the first insertion layer, at a position corresponding to the lower gate electrode, the channel layer including an oxide semiconductor material; and a source electrode and a drain electrode formed to be electrically connected to both ends of the channel layer, respectively.