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公开(公告)号：US20220173945A1
公开(公告)日：2022-06-02
申请号：US17108912
申请日：2020-12-01
Applicant: Silicon Laboratories Inc.
Inventor： Wentao Li , Michael A. Wu , Yan Zhou
Abstract: A mixer in a receiver converts a sounding sequence of alternating ones and zeros to an intermediate frequency signal. A digital mixer converts the intermediate frequency signal to a baseband signal that contains a positive tone and a negative tone. A frequency offset correction circuit generates frequency offset corrections based on frequency offset estimates of the frequency offset between a transmitter of the sounding sequence and the receiver. A frequency adjustment circuit adjusts a frequency of the mixer or the digital mixer to thereby center the positive tone and the negative tone around DC. DFT circuits perform single bin DFTs respectively centered on the positive and negative tones. Phases of the positive and negative tones are calculated based on outputs of the DFT circuits and the phases are used to determine fractional time value associated with a distance measurement between the transmitter and receiver.
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公开(公告)号：US10389482B2
公开(公告)日：2019-08-20
申请号：US15370693
申请日：2016-12-06
Applicant: Silicon Laboratories Inc.
Inventor： Hendricus de Ruijter , Ping Xiong , Wentao Li
Abstract: An apparatus includes a radio frequency (RF) receiver, which includes a differentiator to differentiate a phase signal to generate a differentiated signal. The RF receiver further includes a correlator coupled to receive and correlate the differentiated signal, and a memory to receive and store the differentiated signal. Samples of the differentiated signal are provided to the correlator and to the memory synchronously.
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公开(公告)号：US10230345B1
公开(公告)日：2019-03-12
申请号：US15692321
申请日：2017-08-31
Applicant: Silicon Laboratories Inc.
Inventor： Guner Arslan , Wentao Li
Abstract: In one example, a receiver includes: a low noise amplifier (LNA) to receive and amplify a radio frequency (RF) signal, the LNA having a first controllable gain; a mixer to downconvert the RF signal to an intermediate frequency (IF) signal; a programmable gain amplifier (PGA) coupled to the mixer to amplify the IF signal, the PGA having a second controllable gain; a digitizer to digitize the IF signal to a digitized signal; a digital signal processor (DSP) to process the digitized signal; a first detector to output a first detection signal having a first value in response to the IF signal exceeding a first threshold during a first detection period; and a controller to dynamically update a gain setting of one or more of the LNA and the PGA in response to the first detection signal.
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公开(公告)号：US10061740B2
公开(公告)日：2018-08-28
申请号：US14080405
申请日：2013-11-14
Applicant: Silicon Laboratories Inc.
Inventor： Hendricus de Ruijter , Wentao Li
CPC classification number: G06F13/4295 , H04J3/1605 , H04L27/22 , H04W56/00
Abstract: A receiver includes first, second, and third signal processors and a controller. The first signal processor provides a first signal in response to detecting a first attribute of a received signal. The second signal processor provides a second signal in response to detecting a second attribute of the received signal. The third signal processor provides a third signal in response to detecting a third attribute of the received signal and provides packet data. The controller enables the first signal processor in response to a receive enable signal, controls the third signal processor to provide the packet data in response to receiving the first signal and the third signal, and initializes the first signal processor and the third signal processor in response to receiving the first signal and the second signal.
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公开(公告)号：US20150030061A1
公开(公告)日：2015-01-29
申请号：US13949837
申请日：2013-07-24
Applicant: Silicon Laboratories Inc.
Inventor： Hendricus de Ruijter , Wentao Li
IPC: H04L27/22
CPC classification number: G06F13/4295 , H04J3/1605 , H04L27/22 , H04W56/00
Abstract: A receiver includes a phase click detector, a controller, and a comparator. The phase click detector detects phase clicks in an input signal, where a phase click corresponds to a change in phase of at least a first threshold. The controller is coupled to the phase click detector for calculating a number of phase clicks within one or more time periods. The comparator compares the number of phase clicks within the one or more time periods, and provides an arrival signal if the number of phase clicks is less than a second threshold.
Abstract translation: 接收机包括相位检测器，控制器和比较器。 相位点检测器检测输入信号中的相位点击，其中相位点对应于至少第一阈值的相位变化。 控制器耦合到相位点检测器，用于计算一个或多个时间段内的相位点数。 比较器比较一个或多个时间段内的相位点数，并且如果相位点数小于第二阈值则提供到达信号。
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Patent Agency Ranking
公开(公告)号：US20250151110A1
公开(公告)日：2025-05-08
申请号：US19016567
申请日：2025-01-10
Applicant: Silicon Laboratories Inc.
Inventor： Terry L. Dickey , Yan Zhou , Wentao Li , Rangakrishnan Srinivasan
IPC: H04W74/0808 , H04L5/00 , H04W4/23 , H04W4/80 , H04W74/04
Abstract: A wireless communication device has a receiver to listen to a sequence of channels. A controller responds to a preamble being detected on a first channel while the receiver is tuned to the first channel by causing the receiver to stay on the first channel and decode packet(s) associated with the preamble. The controller responds to detection of a first symbol of a first transmission protocol and the preamble not being detected to cause the receiver to stay on the first channel for a predetermined time waiting for a retry. The controller responds to detection of a second symbol of a second transmission protocol and the preamble not being detected to cause the receiver to switch to an advertising channel of the second transmission protocol. If no preambles, noise, or symbols are detected, the receiver switches to listening to a next channel in the sequence after a fixed time.
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公开(公告)号：US20250007770A1
公开(公告)日：2025-01-02
申请号：US18217019
申请日：2023-06-30
Applicant: Silicon Laboratories Inc.
Inventor： Wentao Li , Yan Zhou , Terry Lee Dickey
IPC: H04L27/26 , H04L5/00 , H04L25/497
Abstract: A demodulator has a correlator bank with multiple correlators. The correlator bank has multiple configurations, including a signal arrival configuration, a coarse timing configuration, and a despreading configuration. The various configurations are used to correlate function transformations of received symbols to template signals. Each correlator has elements with a number of delay blocks corresponding to a number of chips in a symbol. The output of each delay block is multiplied by a bit of a template signal by negating or not negating the output and the multiplications results are summed. A function transformations block receives phase information to generate the function transformations, which are supplied to the correlators. The function transformations include a transformation with a one chip differential, transformations with multi-chip differentials, an average transformation that includes an average of a one-chip phase difference between two adjacent samples, and a second order phase differentiation used for frequency deviation correlation.
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公开(公告)号：US20230337160A1
公开(公告)日：2023-10-19
申请号：US18215488
申请日：2023-06-28
Applicant: Silicon Laboratories Inc.
Inventor： John M. Khoury , Yan Zhou , Michael A. Wu , Wentao Li
IPC: H04W56/00
CPC classification number: H04W56/0035 , H04W56/005 , H04W4/023
Abstract: In at least one embodiment, a method for measuring a distance between a first communications device including a first local oscillator and a second communications device including a second local oscillator includes unwrapping N phase values to generate N unwrapped phase values. N is an integer greater than one. Each of the N phase values indicate an instantaneous phase of a received signal. The method includes averaging the N unwrapped phase values to generate an average phase value. The method includes wrapping the average phase value to generate a final phase measurement of the first local oscillator with respect to the second local oscillator.
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公开(公告)号：US11777548B1
公开(公告)日：2023-10-03
申请号：US17743047
申请日：2022-05-12
Applicant: Silicon Laboratories Inc.
Inventor： Wentao Li , Yan Zhou , Terry L. Dickey
Abstract: A receiver concurrently demodulates data transmitted with a plurality of protocols. The receiver utilizes multiple and simultaneous protocol detections at preamble and/or packet payload phases. To provide robust detection and achieve fewer false detections, the receiver extends the cross correlation length once a short cross-correlation is valid. The receiver includes a first demodulator path and a second demodulator path with different filter bandwidths. The second demodulator path includes a decimator that reduces data by two. A correlator bank is coupled to the first and second demodulator paths and concurrently detects preamble symbols associated with a plurality of protocols. A first noise detector is coupled to the first demodulator path and a second noise detector is coupled to the second demodulator path. A first symbol identifier circuit is coupled to the first demodulator path and a second symbol identifier circuit coupled to the second demodulator path to provide packet payload symbol detection.
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公开(公告)号：US11638116B2
公开(公告)日：2023-04-25
申请号：US17108908
申请日：2020-12-01
Applicant: Silicon Laboratories Inc.
Inventor： Wentao Li , Yan Zhou , Michael A. Wu
IPC: H04W4/02 , G01R23/175 , H04L43/0852 , G01S11/02
Abstract: A receiver includes a first discrete Fourier transform (DFT) block to perform a first single tone DFT on a positive tone associated with a sounding sequence. A second DFT block performs a second single tone DFT on a negative tone associated with the sounding sequence. A DFT coefficient generation block generates first DFT coefficients based on a nominal frequency of the positive tone and an estimated frequency offset between a transmitter frequency and a receiver frequency. The DFT coefficient generation block generates second DFT coefficients based on a nominal frequency of the negative tone and the estimated frequency offset. Multipliers in the DFT blocks multiply I and Q values of the sounding sequence with the coefficients. Accumulators in the DFT blocks accumulate multiplier outputs. An arctan function receives averaged accumulated values from the first and second DFT blocks and supplies first and second phase values used to calculate fractional timing.
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