公开(公告)号：US09397824B1

公开(公告)日：2016-07-19

申请号：US14686203

申请日：2015-04-14

Applicant: Texas Instruments Incorporated

Inventor： Reza Hoshyar ,  Kevin Zheng ,  Nirmal Warke ,  Ali Kiaei ,  Ahmad Bahai

IPC: H04L27/00 ,  H04L7/04 ,  H04L7/00 ,  H04L25/03

CPC classification number: H04L25/03057 ,  H04L7/0004 ,  H04L7/0016 ,  H04L7/0087 ,  H04L7/033 ,  H04L7/0331 ,  H04L7/042 ,  H04L25/03019 ,  H04L25/03261 ,  H04L25/03267 ,  H04L25/03885 ,  H04L27/01 ,  H04L27/34 ,  H04L2025/03363 ,  H04L2025/03484 ,  H04L2025/0349 ,  H04L2025/03636

Abstract: A device and method for providing clock data recovery (CDR) in a receiver is disclosed. The method comprises receiving a Phase Amplitude Modulation (PAM) signal; on startup, using a non-return-to-zero (NRZ)-based phase frequency detector (PFD) to acquire signal frequency from the received PAM signal; and responsive to a determination, switching to a PAM phase detector (PD) for steady state operation.

Abstract translation: 公开了一种用于在接收机中提供时钟数据恢复（CDR）的设备和方法。 该方法包括接收相位调制（PAM）信号; 在启动时，使用不归零（NRZ）的相位频率检测器（PFD）从接收到的PAM信号中获取信号频率; 并且响应于确定，切换到用于稳态操作的PAM相位检测器（PD）。

公开(公告)号：US20130038365A1

公开(公告)日：2013-02-14

申请号：US13654051

申请日：2012-10-17

Applicant: Texas Instruments Incorporated

Inventor： Xiang Gao ,  Ahmad Bahai ,  Mounir Bohsali ,  Ali Djabbari ,  Eric Klumperink ,  Bram Nauta ,  Gerard Socci

IPC: H03L7/08

CPC classification number: H03L7/091

Abstract: A sampling phase locked loop (PLL) circuit includes a pull-up/down buffer configured to convert an oscillator reference clock into a square wave sampling control signal input to a sampling phase detector. The buffer circuit is configured to reduce power by controlling the switching of the pull-up and pull-down transistors (and thereby the transitions of the sampling control signal) so that the transistors are not on at the same time.

Abstract translation: 采样锁相环（PLL）电路包括被配置为将振荡器参考时钟转换为输入到采样相位检测器的方波采样控制信号的上拉/下降缓冲器。 缓冲电路被配置为通过控制上拉和下拉晶体管的切换（以及因此采样控制信号的转换）来降低功率，使得晶体管不同时接通。