公开(公告)号：US20180212839A1

公开(公告)日：2018-07-26

申请号：US15878978

申请日：2018-01-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Todd Christopher HIERS ,  Chunhua HU

IPC: H04L12/24 ,  G06F3/0486 ,  G06F3/0483

CPC classification number: H04L41/22 ,  G06F3/0483 ,  G06F3/0486 ,  G06F17/5045 ,  H04L41/12

Abstract: An architecture-specific web-based executable specification tool maintains specification information and metadata for chip and system on a chip (SoC) design. Metadata available in the development ecosystem may be leveraged to improve the specification-to-design process. A unified, integrated environment for subsystem creation, SoC integration, and SoC specification teams is presented using a tool that comprehends SoC constructs. A modern web-based framework (not stand-alone tool) provides collaboration capabilities and allows visual representation and manipulation of data. Connection fabrics (e.g., network on a chip (NoC)) and other project-specific infrastructure can be configured and synthesized on demand and brought in to the design using the common environment. Netlists and other connectivity data can be fed into automated RTL generation processes directly, or used as a reference for implementation design teams. Reports and automated software generation satisfy the needs of the design verification and software teams. Functional and performance testing feedback loops are also provided.

公开(公告)号：US20250030494A1

公开(公告)日：2025-01-23

申请号：US18909428

申请日：2024-10-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Chunhua HU ,  Venkateswar Reddy KOWKUTLA ,  Eric HANSEN ,  Denis BEAUDOIN ,  Thomas Anton LEYRER

IPC: H04J3/06 ,  H04L7/00

Abstract: A system on a chip (SOC) is configured to support multiple time domains within a time-sensitive networking (TSN) environment. TSN extends Ethernet networks to support a deterministic and high-availability communication on Layer 2 (data link layer of open system interconnect “OSI” model) for time coordinated capabilities such as industrial automation and control applications. Processors in a system may have an application time domain separate from the communication time domain. In addition, each type time domain may also have multiple potential time masters to drive synchronization for fault tolerance. The SoC supports multiple time domains driven by different time masters and graceful time master switching. Timing masters may be switched at run-time in case of a failure in the system. Software drives the SoC to establish communication paths through a sync router to facilitate communication between time providers and time consumers. Multiple time sources are supported.

公开(公告)号：US20230012529A1

公开(公告)日：2023-01-19

申请号：US17946675

申请日：2022-09-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Chunhua HU ,  Sanand PRASAD

IPC: G06F13/28 ,  G06F13/42

Abstract: A method includes transmitting first data with a first priority through a first dedicated interface on a transmit side of a PCIe system. The method also includes transmitting second data with a second priority through a second dedicated interface on the transmit side of the PCIe system. The method includes transmitting the first data and the second data to a receive side of the PCIe system using two or more virtual channels over a PCIe link, where the first data uses a first virtual channel and the second data uses a second virtual channel.